Senior AMS Layout Engineer - LPDDR PHY

About the Role

Micron Technology is a global leader innovating memory and storage solutions that accelerate transforming information into intelligence. We are seeking a Senior AMS (Analog and Mixed Signal) Layout Engineer specialized in LPDDR PHY designs to join our Hyderabad team. This position involves designing critical analog and mixed-signal blocks with an emphasis on robustness, signal integrity, and manufacturing readiness.

Key Responsibilities

• Lead the custom analog and mixed-signal layout for essential LPDDR PHY blocks such as datapath, bias networks, IO analog frontends, and reference circuits, ensuring robustness over process, voltage, temperature (PVT) variations and minimizing noise and mismatch.
• Execute high-speed LPDDR interface layouts addressing complex signal integrity challenges including skew control, impedance matching, shielding, crosstalk reduction, and jitter sensitivity for advanced semiconductor nodes.
• Design and refine array-based layouts for LPDDR data byte lanes (DQ/DQS), command/address lanes, and replica signal paths maintaining symmetry, pitch consistency, repeatability, and scalability across multiple bytes and channels.
• Implement custom digital block layouts within LPDDR PHY like training and calibration logic, test circuits with balanced clocking and congestion management that coexist with sensitive analog regions.
• Collaborate closely with circuit designers to perform layout-aware co-design ensuring compliance with timing, noise, IR drop, and electromigration requirements while integrating parasitic awareness early in the cycle.
• Apply best practices in power distribution, grounding, isolation techniques including guard rings, deep-N-well usage, intelligent decoupling, and domain partitioning to shield critical analog and high-speed signals.
• Perform design rule checking (DRC), layout versus schematic (LVS) verification, parasitic extraction reviews and correlate layout to simulation results for silicon accurate LPDDR block performance.
• Support post-layout optimizations and engineering change orders (ECO), resolving issues affecting margins, yield, and manufacturability, ensuring adherence to JEDEC standards.
• Work in cross-functional teams including architecture, verification, and silicon debug to drive first-silicon success and scalable manufacturing of LPDDR products.
• Contribute to power, performance, and area optimizations focusing on low-power operation, area efficiency, and reliability tailored to LPDDR applications.
• Cultivate knowledge sharing and continuous improvement through developing VXL-compatible layout flows, best practices, and rigorous design reviews.
• Utilize AI and machine learning knowledge to enhance layout automation, data-driven optimization, debugging, and correlation workflows.

Educational Qualifications

• Bachelor of Technology or Engineering degrees in Electronics, Electronics & Communications, or VLSI Engineering
• Master of Technology in Electronics Engineering, Microelectronics or VLSI Engineering

About Micron Technology, Inc.

Micron is a pioneer in industry-leading memory and storage technologies powering innovation in AI, 5G, data centers, and client devices. Our products include DRAM, NAND, and NOR memory under Micron® and Crucial® brands. We foster a diverse and inclusive environment, adhering to all labor laws and ethical recruiting standards.

Equal Opportunity and Ethics

We provide equal employment opportunities without discrimination and prohibit child labor, recruitment fees, or unlawful candidate payments. Candidates are encouraged to truthfully enhance their resumes using AI tools; misrepresentation leads to disqualification. Beware of fraudulent job offers and verify legitimacy through Micron's official channels.