Principal Design Engineer - High Speed SERDES Analog Design

About Cadence

Cadence has been a leader in electronic design and computational software solutions for over three decades, enabling the transformation of design ideas into tangible products. The company serves top-tier global innovators in markets including consumer electronics, hyperscale computing, 5G, automotive, aerospace, industrial, and healthcare.

Position Overview

The Principal Analog Design Engineer will serve as a technical leader on the PMA design team within the SERDES Product Team based in Cork, Ireland, reporting to the Design Engineering Group Director.

Key Responsibilities

• Design high-speed SERDES products capable of supporting data rates up to and beyond 112 Gbps utilizing advanced technology nodes such as 5nm FinFET CMOS.
• Develop analog and mixed-signal integrated circuit blocks from conceptual specification stages through to final verification ensuring compliance with customer requirements.
• Collaborate closely with Physical Design Engineers to integrate IC circuit blocks and PMA sections efficiently.
• Provide technical leadership in circuit design and SERDES architecture within the team.
• Coordinate effectively with global teams located on both the US East and West coasts across different time zones.

Candidate Qualifications

• At least 7 years of professional experience in CMOS SERDES or high-speed I/O integrated circuit design and development.
• A degree in Engineering at Bachelor’s, Master’s, or PhD level.
• Strong familiarity with various SERDES standards and associated electrical specifications.
• In-depth understanding of jitter phenomena and signal equalization methodologies.
• Proficient in designing multiple SERDES circuit blocks including Drivers, Receivers, Serializers, Deserializers, Phase Interpolators, Low jitter PLLs, High Speed Clock Distribution, Bias and Bandgap circuits, Voltage Regulators.
• Excellent analytical, analog design aptitude, clear communication skills, and ability to collaborate in a team-oriented environment.

Additional Skills and Preferences

• Experience using Cadence design tools.
• Design expertise with circuits operating above 10 Gbps.
• Hands-on lab testing experience related to silicon evaluation is a plus.
• Interest in academic contributions such as publishing papers or presenting at conferences like ISSCC or JSSC.

Additional Information

Cadence is fully committed to equal opportunity and fostering a diverse and inclusive workplace culture. Expected travel is minimal, at less than 5%.

Join us to engage in impactful engineering challenges that address complex technological problems.