Physical Design Lead (Full Chip)

About the Company

7Rays Semiconductors specializes in comprehensive VLSI design solutions, assisting clients to achieve excellence in execution. Their expertise encompasses architecture, RTL design, verification, validation, physical design, implementation, and post-silicon validation by applying the latest technologies and practices in semiconductor design.

Collaborating closely with clients, the company builds strong partnerships focused on delivering customized high-quality semiconductor engineering solutions. 7Rays has established a reputation for successful project execution and innovation in the semiconductor manufacturing industry.

Job Overview

The role is for a Coherency Senior Physical Design Engineer focused on full chip design. Candidates are expected to have 7 to 12+ years of experience in physical design, located at the Bangalore office, working on-site.

Key Responsibilities and Expertise Required

• Extensive experience in Floorplanning for System-on-Chip (SoC) designs using Cadence Innovus.
• Designing and implementing IO rings following design specifications.
• In-depth understanding and application of ESD (Electrostatic Discharge), latch-up prevention techniques, and foundry requirements as well as placement strategies.
• Hierarchical design implementation skills including partitioning, hierarchical modules (HMs), tiles, and pushing down designs to each core or tile.
• Knowledge of power grid (PG) creation strategies and pushing down methodologies.
• Understanding analog component placement requirements per design specifications.
• Proficiency in redistribution layer (RDL) technology and packaging considerations essential for SoC floorplanning.
• Ability to independently perform floorplan physical verification cleanup including sign-offs for physical verification, ESD, and foundry/analog compliance.
• Advanced scripting capabilities in TCL, Perl, and Makefile for managing and troubleshooting place & route (P&R) flows and flow automation.
• Experience with complex algorithmic development to manage sign-off processes and regression testing for P&R tools.
• Familiarity with sign-off issues such as metal fill, spare cells, design for manufacturability (DFM) rules, and boundary cells tailored to latest process technologies.
• Problem-solving aptitude, proactive engagement, hardworking attitude, and strong interpersonal communication skills.

Educational Qualifications

A Bachelor's degree in Electrical Engineering, Electronics, or Computer Engineering is required.