Package Architect
Tsavorite Scalable Intelligence
Greater Bengaluru Area · Full Time
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- Experience
- 16+ yrs
- Salary
- —
- Openings
- 1
- Posted
- 6 days ago
- Work mode
- In office
- Resume
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Job description
About Tsavorite Scalable Intelligence
Established in 2023 by seasoned industry experts with headquarters in California, Tsavorite Scalable Intelligence is a Bangalore-based product-driven startup. Our expertise lies in developing chipset and intelligent machines tailored for scalable enterprise AI solutions, including streaming video intelligence, training of trillion-parameter models, and fine-tuning large language models (LLMs). Our innovations empower enterprises to enhance productivity through cutting-edge technologies. We are the first company globally to develop Agentic Silicon designed to drive the future of AI. Our mission centers on accelerating enterprise AI adoption end-to-end, spanning from edge devices to Zettascale computing systems. Our pioneering software and modular silicon chiplets are set to revolutionize how AI models are trained, deployed, and scaled.
Position Overview
We are expanding our talented team at Bangalore and seek an experienced Package Architect to lead the design of advanced AI product packaging solutions.
Key Responsibilities
- Design and develop flip chip BGA packages for cutting-edge AI products.
- Conduct feasibility analyses for new IP definitions and packaging concepts.
- Fully own substrate layout designs end-to-end and manage multiple tape-outs.
- Engage in co-design efforts across silicon, packaging, and printed circuit boards.
- Collaborate closely with signal integrity, power integrity teams, PCB design, mechanical, and thermal experts to optimize products according to specifications.
- Liaise with OSAT/packaging vendors to understand design constraints, review designs for manufacturability, ensure DFM compliance, and document bills of materials.
Preferred Qualifications and Skills
- Over 16 years of professional experience specializing in flip chip BGA package design.
- Expertise in large form factor, multilayer designs, including stack-up definitions, bump and ball map planning, and package outline drawings.
- In-depth understanding of package design rules, design for manufacturability (DFM), and a proven record of successful tape-outs.
- Strong knowledge of package-level signal integrity and power integrity principles.
- Hands-on experience with high-speed SerDes protocols such as PCIe Gen6 and 112-224G Ethernet along with memory interfaces including DDR5, LPDDR, and HBM.
- Additionally, mentorship and experience with Mentor Xpedition software tools are advantageous.
Additional Information
We offer a unique opportunity to work at the forefront of AI silicon innovation within a dynamic startup environment focused on scalable enterprise AI solutions.