Engineer

Job Overview

This role requires significant expertise in timing activities within ASIC physical design, including library, LVF, and various timing sign-off tasks. The ideal candidate will work extensively with CAD tools and timing sign-off methodologies, correlate results with Spice simulations, and possess a detailed understanding of library characterization and physical implementation processes.

Responsibilities

• Perform timing-related tasks such as library characterization, LVF, AOCV/POCV/SOCV management and sign-off.
• Use CAD tools to correlate different timing sign-off tools with Spice simulations focusing on timing, noise, Monte Carlo analyses, etc.
• Engage hands-on in standard cell library characterization and deeply understand the characterization process and flow.
• Automate workflows and develop new processes to increase team productivity using scripting languages including Python, Perl, TCL, and Bash.
• Apply working knowledge of Spice extraction, modeling, and aging reliability models at advanced technology nodes.
• Stay current with latest technology nodes and physical design practices such as Place and Route (P&R) and Static Timing Analysis (STA) sign-off.
• Demonstrate willingness to learn and contribute to developing and validating new design methodologies.

Requirements

• Between 1 to 3 years of hands-on experience in characterization, timing, power analysis, and pin-capacitance library modeling specifically for Analog and GPIO blocks.
• Functional understanding of GPIO and Analog IP characterization.
• Preferred experience with characterization tools and simulators like Silicon Smart, Hspice, Primesim, AFS, Spectre, and Liberty format descriptions.
• Strong self-motivation, effective teamwork capabilities, and excellent communication skills.
• Proficiency in Python programming with a solid scripting skillset providing added value.
• Experience with ASIC physical design tools including DesignCompiler, IC Compiler II (ICC2), FusionCompiler, PrimeTime, StarRC, Innovus, covering synthesis, floorplanning, power planning, placement, CTS, routing, and STA.