Digital ASIC Design Engineer

Position Overview

Our client, an established semiconductor company specializing in chip IP for consumer electronics, seeks a Digital ASIC Design Engineer to join their design team. This position involves creating custom digital blocks embedded in everyday devices such as phones, wearables, and connected vehicles.

Key Responsibilities

• Design and develop digital logic blocks intended for chip integration.
• Perform verification of designs using test benches, identifying and resolving bugs.
• Manage synthesis and timing closure using standard EDA signoff tools.
• Analyze power consumption and contribute to low-power design strategies.
• Develop scripts and tools (primarily in Python) to enhance team workflows.
• Collaborate with cross-functional engineering teams and support release management processes.

Candidate Requirements

• A degree in engineering or a related scientific discipline.
• Proven proficiency with RTL design, particularly in SystemVerilog, alongside scripting skills in Python, Tcl, or Perl.
• At least two years of professional experience in digital RTL design.
• Experience with tooling such as synthesis, Logic Equivalence Checking (LEC), and static timing analysis tools like PrimeTime/PTPX or equivalents.
• Desirable skills include experience with ECO fixes, Design Rule Check (DRC), Clock Domain Crossing (CDC) checks, C++/SystemC programming, and design for testability methods including MBIST.
• Strong communication skills and the ability to work efficiently within a collaborative team environment.

Additional Information

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