DFT Manager

About Marvell

Marvell creates semiconductor solutions essential for the data infrastructure connecting the modern world. Serving domains such as enterprise, cloud and AI, and carrier architectures, their pioneering technology enables groundbreaking opportunities. Employees at Marvell influence individual lives, enhance entire industries, and drive transformative innovation. The company fosters a thriving environment for learning and leadership among those eager to make a lasting impact.

Role Overview

The DFT Manager is accountable for defining, implementing, and overseeing Design for Test (DFT) strategies within complex silicon projects. This position ensures optimal test coverage, manufacturability, and product quality while balancing cost, timeline, and performance factors. The manager leads a team of DFT engineers and collaborates cross-functionally with design, verification, manufacturing, product engineering, and external partners.

Key Responsibilities

• Define the comprehensive DFT architecture and approach for SoCs, ASICs, or IP blocks across multiple initiatives.
• Develop and uphold DFT best practices, automation procedures, and supporting documentation.
• Lead the planning, integration, and validation of DFT elements including full scan, compression, EDT scan, ATPG and fault modeling (stuck-at, transition, cell-aware, path delay), logic and memory BIST, boundary scan (IEEE 1149.x), IJTAG, and DFT for IOs and analog elements.
• Ensure superior test coverage while minimizing impacts on area, power, and timing.
• Guide testability requirements from early architecture stages through to tape-out.
• Approve DFT readiness at critical milestones such as RTL freeze, netlist completion, and tape-out.
• Work closely with design and physical teams to resolve timing, congestion, and implementation challenges related to DFT.
• Partner with product engineering and manufacturing teams for silicon bring-up, yield analysis, and volume production.
• Collaborate with ATE and test program teams for delivering and deploying test patterns.
• Manage and mentor a team of DFT engineers, overseeing technical guidance, design reviews, performance evaluations, and career progression.
• Engage with EDA vendors regarding tool usage, workflows, and feature needs.

Required Qualifications and Experience

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• Over 8 years of hands-on experience in DFT with progressively greater technical or leadership roles.
• In-depth knowledge of scan architectures and ATPG techniques.
• Expertise in memory and logic BIST implementations.
• Experience in fault coverage analysis and debugging.
• Competence in DFT insertion and verification procedures.
• Strong foundation in digital design and verification principles.
• Understanding of timing, power, and physical design interactions.
• Familiarity with silicon manufacturing and test processes.
• Proficiency using Tessent EDA tools.
• Track record of managing designs from concept to successful production.

Preferred Qualifications

• Previous experience managing people or leading technically.
• Skilled in scripting languages like Tcl and Python for automation tasks.
• Experience working with advanced semiconductor nodes and low-power design techniques.
• Exposure to heterogeneous designs such as multi-die, chiplets, or mixed-signal SoCs.
• Excellent communication abilities with proven influence across cross-functional groups.

Compensation and Benefits

The anticipated annual base salary range is CAD 142,100 to 189,400. Alongside competitive pay, Marvell offers excellent benefits and a work culture emphasizing collaboration, transparency, and inclusion. The company commits to providing tools and resources to empower employees to succeed and develop their careers.

Diversity and Inclusion

Marvell provides equal employment opportunities to all applicants regardless of race, color, religion, sex, nationality, sexual orientation, gender identity, disability, or veteran status.

Interview Policy

Candidates must not employ AI tools (such as transcription apps or real-time answer generators) during interviews. Use of such tools without authorization will lead to disqualification. Interview evaluations focus on individual skills, experience, and communication in real time.

Legal and Compliance

This role may require access to technology governed by U.S. export control laws, including the Export Administration Regulations. Applicants must meet eligibility criteria for access to export-controlled information, which may involve a licensing review process. Only U.S. citizens, lawful permanent residents, or protected individuals are exempt from this process.

Technology Use in Hiring

Marvell may apply artificial intelligence technologies to assist in application evaluations but ensures meaningful human involvement in all hiring decisions without sole reliance on automation.