Staff Physical Design Engineer

Role Overview

Credo invites applications for the position of Staff Physical Design Engineer to join its Digital R&D team at the Singapore office. The successful candidate will spearhead the comprehensive physical design and implementation activities for SoC projects, working in close collaboration with frontend and physical design/integration teams located in China and Taiwan, ensuring successful tape outs.

About Credo

Credo's mission centers on revolutionizing connectivity at scale through high-speed, reliable, and energy-efficient system solutions. Their product lineup includes ZeroFlap Active Electrical Cables, ZeroFlap optical transceivers, OmniConnect memory solutions, and advanced retimers and DSPs tailored for optical and copper Ethernet and PCIe. These offerings are integrated with the PILOT diagnostic and analytics software platform, enabling customers to connect critical global systems.

Credo fosters an inclusive workplace welcoming applicants regardless of race, color, religion, gender, sexual orientation, national origin, genetic information, age, disability, veteran status, or other legally protected characteristics. Accommodations are available upon request during the application process.

Responsibilities

• Lead top-level, IP, and block-level physical implementation from RTL to GDSII focusing on optimizing timing, power, and area for high-speed SerDes and interconnect subsystems.
• Participate in defining physical design methodologies, automating design flow, managing chip floorplanning, power and clock distribution, power planning and analysis, place-and-route processes, physical verification, and sign-off.
• Carry out static timing analysis, power and noise evaluations, and physical verification tasks.
• Deliver IP hardening, integration, and verification phases.
• Collaborate closely with frontend and integration teams to assure timely and successful tape outs.

Basic Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or Computer Science.
• At least 8 years of recent, hands-on experience as a Physical Design Engineer.
• Proficiency with hierarchical physical design strategies and methodologies.
• Experience working with 5nm and more advanced technology nodes.
• Track record of independently managing chip-level place-and-route and delivering complex SoC tape outs under demanding schedules.
• Expertise with EDA tools including Cadence Innovus and Synopsys Fusion Compiler.
• Strong knowledge of static timing analysis tools such as PrimeTime or Tempus; power and reliability analysis tools like PTSI, Voltus, and Redhawk; and extraction tools including Quantus and StarRC.
• Familiarity with design rule checking, antenna, layout versus schematic, and electrical rule check tools such as Calibre.