Verification Lead

Position Overview

We are seeking an experienced Verification Lead with over 11 years of hands-on experience in SystemVerilog and UVM to lead the verification efforts for blocks, subsystems, or SoCs at one of India's top IT companies based in Kochi, Kerala.

Key Responsibilities

• Lead and manage the verification process for blocks, subsystems, or entire SoCs.
• Oversee a team of engineers to ensure timely delivery of verification objectives.
• Develop comprehensive test plans and testbenches.
• Execute high-quality constrained random UVM tests to achieve coverage goals efficiently.
• Conduct thorough debugging and troubleshooting across all stages of the verification flow, including gate-level simulations.
• Utilize various EDA and revision control tools to support verification activities.

Technical Expertise

• Proficient in verifying IPs, subsystems, and SoCs using SystemVerilog/UVM methodologies.
• Expertise in verifying one or more of the following interfaces or domains: PCI Express, UCIe, CXL, NVMe, AXI, ACE, CHI, Ethernet, RoCE, RDMA, DDR, LPDDR, HBM, ARM, RISC-V CPU based subsystems or SoCs.
• Familiarity with power-aware simulations using UPF techniques.
• Experience with EDA tools such as VCS, Verdi, Cadence Xcelium, Simvision, and Jasper.
• Use of revision control systems including Git, Perforce, and Clearcase.
• Desirable knowledge of SystemVerilog Assertions (SVA), formal verification, and scripting with Python, Perl, or TCL.

Additional Information

This role is based onsite in Kochi, Kerala. Candidates should be prepared to lead verification teams and own the verification lifecycle for complex SoC designs.