Staff Engineer, Analog Layout

About Ambiq

Ambiq is committed to enabling intelligence everywhere by driving the AI edge revolution through ultra-low power semiconductor solutions. Utilizing proprietary sub-threshold and near-threshold technologies, Ambiq’s chips deliver significant energy efficiency improvements without relying on expensive process scaling. Since 2010, over 300 million units have been shipped for use in innovative wearables, medical devices, IoT gadgets, and AI-enabled edge applications. Ambiq operates globally with teams spanning design, research, development, production, marketing, sales, and operations, including a key presence in Singapore.

At Ambiq, employees embody five core values: Innovate, Collaborate, Focus, Learn, and Achieve. They seek self-driven, inventive problem solvers eager to push technological boundaries and significantly impact energy efficiency.

Role Scope

As a Staff Engineer specializing in Analog Layout, you will lead the physical implementation of critical analog subsystems such as PMUs, clocking modules, and data converters. Your work will convert circuit architectures into silicon-ready layouts that meet demanding benchmarks for performance, die area, device matching, and long-term reliability. Collaboration with the analog design and RTL/Physical Design teams is essential to develop custom layouts aligning with client requirements. You will work on cutting-edge semiconductor technologies including 22nm, 12nm, and beyond.

Ideal candidates are experienced, versatile professionals who have progressed through multiple design cycles and possess comprehensive knowledge of layout workflows—from initial floorplanning and close collaboration with designers through detailed layout, parasitic extraction, design rule checks (DRC), layout versus schematic (LVS) closure, tape-out, and support for validation and production testing. This position requires your physical presence onsite in Singapore five days per week.

Key Responsibilities

• Collaborate with analog designers on floorplanning and devise layout strategies at both chip and block levels.
• Make architectural layout decisions that optimize trade-offs between performance, device matching, area efficiency, and reliability.
• Perform transistor-level analog integrated circuit layout focusing on critical matching, shielding, and parasitic-sensitive elements.
• Lead complex block layout efforts and oversee or review work from other layout engineers to ensure quality and conformance.
• Conduct detailed layout design reviews, managing and resolving any follow-up action items.
• Participate in circuit design reviews offering guidance on layout feasibility and providing feedback to designers and layout engineers.
• Work across analog and digital design teams to confirm layouts satisfy intended circuit functionality and interface specifications.
• Manage parasitic extraction, LVS, DRC, antenna effect mitigation, and fill techniques for assigned blocks and integrate top-level designs.
• Assist with prototype chip bring-up and testing to verify analog blocks against layout-induced effects.
• Develop and support manufacturing test plans that consider layout impacts on testability, such as probe accessibility and trim structures.
• Collaborate with Product Engineering to address manufacturing and production requirements related to layout and yield optimization.
• Provide Applications Engineering support by addressing customer inquiries about layout challenges involving matching, noise, and reliability issues.