Senior Staff Physical Design Engineer - Floorplanning

About EnCharge AI

EnCharge AI is a pioneer in cutting-edge AI hardware and software systems designed for edge-to-cloud computing scenarios. Their innovative in-memory computing architectures offer exponentially improved compute efficiency and density compared to current top-tier solutions. Coupling high performance with seamless software integration, EnCharge AI aims to unlock AI's full potential within power and space-limited environments. Founded in 2022, the company is led by seasoned semiconductor and AI system experts.

Role Overview

We are looking for an experienced Staff or Senior Staff Physical Design Engineer specializing in Floorplanning to join our Bangalore team on a hybrid schedule (2 days onsite, 3 days remote). This role is fundamental as a technical leader bridging RTL/systems design and final GDSII layout. You will shape chip-top floorplans for complex, large-scale SoCs or sub-chips while balancing power, performance, and area.

Primary Responsibilities

• Lead architectural floorplanning covering macro placement, pin assignment, and defining partitions for multi-million gate projects.
• Conduct comprehensive Analysis of IR-drop (static and dynamic) and Electromigration to diagnose and solve power-related challenges without timing penalties.
• Collaborate directly with RTL and architecture teams employing design thinking to adjust microarchitectural elements—including bus widths, pipeline stages, and memory architectures—to optimize physical design outcomes.
• Develop best practices and automated methodologies for floorplanning and power distribution network (PDN) synthesis for broader team utilization.

Technical Requirements

• Minimum 10 years of physical design experience with a consistent history of tape-out successes at advanced technology nodes such as 7nm, 5nm, or 3nm.
• Expertise in PDN modelling, including complex power-up sequencing and management of multi-voltage domains.
• Proficient with hierarchical floorplanning and top-level chip integration using industry tools like Cadence Innovus or Synopsys IC Compiler II.
• Strong analytical capabilities regarding thermal-aware PDN and physical effects from high current densities.
• Advanced scripting skills in Tcl, Python, or Perl to streamline floorplanning automation and data processing.

Behavioral Attributes

• Exceptional critical thinking with an aptitude to challenge assumptions and uncover latent performance, power, and area optimizations.
• Design thinking approach fostering empathy and holistic understanding between upstream RTL and downstream sign-off teams.
• Strong communication skills to effectively present technical trade-offs and decisions to various stakeholders.

Education

Bachelor’s or Master's degree in Electrical or Electronics Engineering or equivalent.

Additional Information

Location: Bangalore, hybrid work model with two days in-office and three days remote.