Senior Layout Designer

About the Client

Our client is a leading multinational semiconductor company located in Cork City, Ireland.

Role Overview

The Senior AMS Layout Design Engineer will play a pivotal technical leadership role within the PMA custom layout design team, part of a SERDES/UCIe Product Team based in Cork. The position requires onsite presence four days a week.

Core Responsibilities

• Design cutting-edge high-speed SERDES/UCIe products with data rates of 112 Gbps and beyond, utilizing advanced technology nodes such as 3nm FinFET CMOS.
• Create and deliver high-quality layouts for Analog/Mixed-Signal circuit blocks in close cooperation with circuit designers.
• Manage all phases of the back-end design flow, including initial floor planning, detailed layout work, and final verification ensuring compliance with foundry design rules.
• Lead the technical direction of the layout team, overseeing design work from block-level to PHY top-level integration and completion.
• Collaborate effectively with global teams located on the US west and east coasts, accommodating the different time zones.

Experience and Expertise

• At least 7 years of hands-on experience in CMOS SERDES or high-speed I/O IC layout design and development.
• Strong proficiency in layout design for multiple SERDES circuit blocks, including Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low jitter PLL, High Speed Clock Distribution, Bias and Bandgap, and Voltage Regulators.
• Experience delivering high speed and precision cells, blocks, and IPs efficiently and to a high standard.
• Expertise in PHY GDS architecture and implementation, integrating PMA and PCS hierarchies with optimized clock and power distribution schemes.
• Experience collaborating globally with layout designers, circuit designers, and project managers to meet technical requirements and schedule demands.
• Strong analytical and problem-solving capabilities, excellent analog design aptitude, good communication skills, and proven teamwork abilities.

Educational Qualifications

The candidate should hold a Bachelor of Engineering (BEng), Master of Engineering (MEng), or a PhD degree.

Additional Skills and Preferences

• Experience using Cadence tools and designing at speeds exceeding 10 Gbps within technologies smaller than 40nm.
• Engagement with Cadence R&D teams (working with Virtuoso, PVS development) to advance layout editing and verification tools.
• A keen interest in innovating within the analog/custom layout design methodologies.