Design Verification Manager

About the Role

Our client, a leading multinational semiconductor corporation, is seeking a Digital Design Verification Manager to be based in either Limerick or Cork, Ireland. The position requires physical presence onsite at least three days per week. The successful candidate will oversee and direct the verification process of digital, ASIC, and SoC designs, ensuring that chip functionality aligns perfectly with specifications ahead of tape-out.

Key Responsibilities

• Formulate and implement comprehensive verification methodologies, plans, and progress milestones.
• Create detailed verification plans based on design documents and requirements.
• Set coverage targets and define criteria for project sign-off.
• Lead and mentor a team of verification engineers, managing project allocations and supporting their professional growth.
• Coordinate efforts across multiple verification teams to streamline execution.
• Supervise the development and maintenance of SystemVerilog/UVM testbenches, tests, assertions, and coverage metrics.
• Monitor simulation progress, regression tests, coverage statistics, and bug tracking.
• Lead root-cause analyses for design and verification failures, reviewing critical bugs, and prioritizing resolutions.
• Drive initiatives to improve verification quality, reduce escapes, and enhance efficiency prior to tape-out.
• Collaborate closely with RTL/design, architecture, firmware/software, emulation, FPGA, physical design, and validation stakeholders to resolve ambiguities and coordinate cross-functional dependencies.
• Manage project timelines, resource estimation, risk mitigation, and deliverables tracking.
• Report coverage, bug status, progress, and risks to senior management and assist in tape-out readiness evaluations.
• Champion the adoption of verification methodologies and tools such as automation, constrained-random testing, formal verification, and coverage-driven verification techniques.
• Assess new verification technologies to continuously boost team productivity.

Educational & Professional Qualifications

• PhD, postgraduate degree, or bachelor's degree in Electronic Engineering or a closely related field.
• Minimum 5 years in digital design verification management role.
• Over 10 years of relevant engineering experience.

Skills and Experience Required

• Proven expertise in full-product verification workflows, including hardware and firmware integration.
• Strong background in constrained-random verification environments and building UVM and coverage-driven verification methodologies.
• Experience using SystemVerilog Assertions (SVA).
• Familiarity with verification management tools such as vManager, vPlan, and regression suites.
• Experience on mixed-signal integrated circuits considered advantageous.
• Proficiency in debugging test failures and reporting on verification results to meet defined functional and code coverage targets.
• Extensive utilization of RTL simulation tools.
• Technical skills in UVM, SystemVerilog, and scripting languages including Perl and Python.
• Strong interpersonal and communication abilities to collaborate effectively with cross-functional teams and mentor junior engineers.

Additional Information

The role demands excellent leadership capabilities to support and develop the verification team, as well as hands-on technical expertise to maintain high verification quality standards.