Senior IP Verification Engineer

Role Overview

As a Senior IP Verification Engineer, your primary responsibility will be to verify sophisticated IPs and subsystems including RISCV CPU cores, memory controllers, and interconnects. You will work closely with international design and architecture teams to ensure the correctness of IP modules.

Key Responsibilities

• Perform pre-silicon verification of IP modules or subsystems.
• Develop and define detailed IP verification plans based on product requirements, industry standards, and architectural specifications.
• Collaborate with hardware, firmware, software design teams, as well as architecture and system engineering teams to thoroughly understand the IP or subsystem functions and applications.
• Implement verification plans aligned with product specifications and verification criteria established by product architects.
• Design, build, diagnose, and maintain UVM-based verification environments for RTL simulations.
• Create test cases within suitable verification frameworks, generate stimuli and assertions, execute simulations, debug test cases on multiple design models including RTL, power-aware RTL, gate-level netlists, FPGA and emulation platforms.
• Run regression suites and analyze code and functional coverage results.

Qualifications and Skills

• Bachelor’s degree in Electrical Engineering or Computer Science with a minimum of 5 years experience in IP or Subsystem verification.
• Extensive experience in testbench architecture and development using UVM methodology targeting IP, subsystems, and SoC verification.
• Strong background in microcontroller and microprocessor architectures, system interconnects, and cache coherency protocols.
• Proficient knowledge of protocols such as AHB/AMBA, various memory types including ROM, RAM, Flash, LPDDR, DDR3/4, and associated memory controllers.
• Advanced skills in Verilog, SystemVerilog, C/C++, and shell scripting.
• Familiarity with scripting languages like Perl, TCL, or Python is advantageous.
• Thorough expertise in metric-driven verification techniques encompassing functional and code coverage analysis.
• Strong command of directed tests and constrained random verification methodologies.
• Good understanding of formal verification practices and assertion-based verification.
• Experience in debugging design models both before and after silicon fabrication, across simulation and hardware bench setups.
• Excellent verbal and written communication capabilities.