Microsoft

Senior Formal Verification Engineer

Microsoft

Bengaluru, Karnataka, India · Full Time

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Experience
7+ yrs
Salary
Openings
1
Posted
3 days ago
Work mode
In office
Education
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
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Job description

Role Overview

We are looking for a highly skilled Formal Verification Engineer with over seven years of experience in SoC/IP verification using formal methods. The successful candidate will lead the formal verification approach, build scalable verification environments, write assertions and properties, conduct verification at both architectural and RTL levels, and closely collaborate with architects, designers, and DV teams to assure silicon quality.

Key Responsibilities

  • Formulate and carry out formal verification strategies targeting complex IPs, subsystems, and SoCs.
  • Create formal verification plans guided by architecture and microarchitecture documentation.
  • Develop SystemVerilog Assertions (SVA), formal properties, assumptions, coverage metrics, and checkers.
  • Analyze counterexamples and partner with designers to identify and fix design flaws.
  • Facilitate verification closure by ensuring proof convergence, performing coverage analysis, and advancing methodologies.
  • Build reusable components, libraries, and automate formal verification workflows.
  • Participate in advancing formal verification methodologies including AI-assisted verification and implementing best practices.
  • Guide and mentor junior engineers, reviewing verification plans, assertions, and outcomes.
  • Work collaboratively with teams across Architecture, RTL Design, DV, Emulation, and Silicon Validation disciplines.

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline.
  • More than seven years' semiconductor verification experience with a strong focus on Formal Verification.
  • Solid grasp of Digital Design fundamentals.
  • Understanding of Computer Architecture and System on Chip (SoC) Design.
  • Proficiency in SystemVerilog and SystemVerilog Assertions (SVA).
  • Practical hands-on experience with formal verification tools including Cadence JasperGold and Synopsys VC Formal.
  • Strong debugging capabilities and analytical thinking skills.

Additional Information

The position will remain open for a minimum of five days and will accept applicants until filled. Equal employment opportunity is assured regardless of age, nationality, gender, disability, or other protected characteristics under applicable laws. Assistance with religious and disability accommodations during the hiring process is available upon request.

Level

Senior

Minimum education

Bachelor's Degree

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