Senior Analog Layout Engineer

About the Role

LeadSoc Technologies Pvt Ltd is seeking a Senior Analog Layout Engineer based in Hyderabad. The role demands 4 to 8 years of hands-on experience in custom and analog IC layout, focusing on delivering precise, high-quality physical designs for complex analog and mixed-signal circuits in collaboration with design teams to meet performance, reliability, and area specifications.

Key Responsibilities

• Create custom analog and mixed-signal IC layouts starting from schematic or netlist to the physical layout database.
• Design layouts for analog components including amplifiers, bandgap references, LDOs, ADC/DAC blocks, PLLs, and bias circuits.
• Implement advanced layout techniques such as matching methods, common-centroid configurations, interdigitation, shielding, guard rings, and dummy devices to enhance performance.
• Conduct design rule checks (DRC), layout versus schematic checks (LVS), electrical rule checks (ERC), and parasitic extraction (PEX), addressing any issues found.
• Collaborate extensively with analog design, circuit design, verification, and physical design teams for seamless integration.
• Optimize layouts with emphasis on area efficiency, parasitic minimization, device matching, noise reduction, and overall circuit functionality.
• Troubleshoot post-layout simulation and extraction challenges.
• Support integration and closure of physical verification for top-level and custom blocks.
• Contribute to the development and enhancement of layout methodologies, automation tools, and workflows.

Required Qualifications and Skills

• Between 4 and 8 years of experience in analog or custom IC layout engineering.
• Proficient in Cadence Virtuoso toolset with strong practical skills.
• Solid grasp of CMOS analog layout principles and sophisticated matching techniques.
• Experienced in performing DRC, LVS, ERC, and PEX processes effectively.
• Deep understanding of device physics, parasitic effects, and layout-dependent characteristics.
• Familiarity with deep-submicron and advanced process technology nodes is advantageous.
• Exposure to analog and mixed-signal IC design flows.
• Capability to independently manage layout projects from start to signoff level.
• Excellent problem-solving abilities with strong debugging skills.

Preferred Experience

• Background in layouts for high-performance analog, mixed-signal, power management ICs (PMIC), SerDes, PLLs, or data converters.
• Experience with advanced CMOS processes such as FinFET or gate-all-around (GAA) technology.
• Knowledge of electromigration (EM), IR drop, reliability assessments, and post-layout simulations.
• Skills in scripting and automation using SKILL, Tcl, or Python languages.
• Strong communication skills and ability to work collaboratively across functions and teams.