Senior Analog Layout Engineer

About Ciena and the Role

Ciena is a global leader in high-speed connectivity, dedicated to a people-centric culture that values flexible work environments, personal development, and inclusivity. We combine advanced technology with a strong commitment to social and community impact.

The Wavelogic product family plays a pivotal role in Ciena's fiber-optic transmission systems and is a cornerstone of the company's success in telecom. This team has a history spanning over three decades of innovation in high-speed circuits for broadband fiber-optic modems, including pioneering the first high-speed DAC and ADC analog macros enabling coherent fiber-optic solutions.

We are seeking a diligent Analog Layout Engineer to join our team, focused on cutting-edge high-speed analog circuit layouts in advanced deep-submicron CMOS and/or BiCMOS technologies. Your work will involve developing exceptional layouts for analog macros such as electrical interface DACs and ADCs for 112G and 224G SERDES, high-speed DACs/ADCs interfacing with optical components, transimpedance amplifiers, modulator drivers, and precision analog control circuits.

Core Responsibilities

• Perform layout feasibility studies collaboratively with senior analog designers to identify optimal design solutions balancing multiple trade-offs.
• Develop layouts for assigned analog blocks, following detailed floor planning, component placement, and routing procedures.
• Execute comprehensive verification including DRC, ANT, LVS, PERC, EM, and IR checks to ensure top-tier layout quality.
• Explore and apply new features in layout tools and processes to boost productivity and efficiency.
• Provide frequent progress updates, engage in team discussions, and contribute knowledge-sharing within the group.

Required Qualifications and Skills

• Bachelor's degree in Electrical Engineering or a related discipline, plus 1 to 5 years of professional experience.
• Proficiency in custom analog and mixed-signal layout design with expertise in deep submicron CMOS devices, including FinFET technology.
• Experience in designing custom layouts for Analog/Mixed Signal circuits, such as ADCs, DACs, PLLs, and SERDES.
• Skilled use of industry layout tools like Cadence Virtuoso, Siemens Calibre, and Ansys Totem, with knowledge of advanced node design flows.
• Strong analytical abilities to swiftly identify and resolve layout challenges.
• Expertise in layout methodologies covering floor planning, device matching, parasitic minimization, RF shielding, electromigration, IR drop, ESD protection, and high-frequency interconnect routing.
• Detail-oriented approach ensuring meticulous accuracy and superior design quality.
• Understanding of semiconductor fabrication processes and foundry technologies.
• Adaptability to a dynamic and fast-changing work environment.
• Comprehensive knowledge of RC delay, electromigration, coupling effects, guard rings, DNW, PN junctions, and advanced process phenomena like LOD, OSE, and WPE.
• Strong capability to interpret DRC, PERC, ANT, ERC, and LVS reports.
• Ability to detect vulnerable circuit and layout elements and collaborate with circuit designers to mitigate issues.
• Scripting experience in PERL or SKILL is advantageous but not mandatory.

Compensation and Benefits

The annual salary range for this role in Ottawa, Canada is between 114000 and 182000 CAD. Ciena offers an extensive benefits package including healthcare (medical, dental, vision), retirement plans (DCPP in Canada), employee stock purchase programs, paid holidays, sick leave, vacation time, and compliance with all applicable family and leave laws. Certain employees may be eligible for bonuses or commissions based on role.

Equal Opportunity and Inclusivity

Ciena is committed to fostering an inclusive workplace where employees feel respected and valued, prohibiting discrimination of any form. Accommodations will be provided during the recruitment process upon request.