Principal High-Speed Analog Layout Design Engineer

About Celero Communications

Celero Communications is an innovative semiconductor startup focused on developing cutting-edge coherent DSP technology for the next era of AI infrastructure. Recently, the company secured $275 million in Series C funding after revealing the industry's first 2nm coherent DSP silicon, with backing from Alphabet's CapitalG valuing it at $3 billion. As the company expands, it seeks outstanding professionals across the US, Canada, and Argentina for diverse opportunities.

Role Overview

We are looking for a High-Speed Analog Layout Design Engineer to take charge of the physical layout design of sophisticated analog and mixed-signal IP blocks central to our advanced optical communication systems. This role anchors the Analog & Mixed-Signal design team, focusing on layout development of vital blocks such as ADCs, DACs, PLLs, and other high-performance analog/mixed-signal circuits. The successful candidate will collaborate closely with schematic designers, CAD/PDK teams, and fellow layout engineers to guarantee first-time silicon success. This hands-on position suits a proactive engineer who excels in a fast-moving environment and enjoys mentoring while contributing to innovative chip development.

Key Responsibilities

• Lead end-to-end physical layout design for complex analog/mixed-signal macros, including floor planning and final verification.
• Work closely with schematic designers to develop layout strategies optimizing performance, device matching, symmetry, and reliability.
• Mentor and guide junior layout engineers and contractors across different time zones to uphold best layout and verification practices.
• Conduct and troubleshoot comprehensive hierarchy checks such as LVS, DRC, PERC, ERC, using standard tools like Pegasus and Calibre.
• Assist with chip-level planning, including top-level floor planning, integration of blocks, power grid design, and routing signals.
• Participate in layout review meetings offering technical leadership focused on layout quality, verification thoroughness, and schedule compliance.
• Support automation projects via scripting and customizing tools using SKILL, TCL, and Python where applicable.

Essential Qualifications

• At least 10 years of practical experience in analog/mixed-signal layout design within advanced CMOS/FinFET technologies.
• Demonstrated success in leading top-tier IP layout macros and preparing IPs for handoff to physical design teams.
• Proven leadership managing major IP layout macros or entire chip-level layout at FinFET process nodes, preferably TSMC.
• Minimum one year of hands-on work with TSMC FinFET nodes (N3, N5, N7, or N16).
• In-depth knowledge of device physics, layout-dependent effects (LOD, WPE, OSE, LDE), and their influence on circuit behavior.
• Expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and minimization of parasitics.
• Proficiency in floor planning, hierarchical integration, routing methodologies, and design of power and ground grids.
• Experienced user of Cadence Virtuoso, Calibre, Pegasus, and associated layout/verification tools.
• Familiarity with verification processes including LVS, DRC, PERC, Density, DFM, ERC, and Antenna checks.
• Comfortable working in coordinated remote and international team settings.
• Strong written and verbal communication skills capable of conveying layout trade-offs and project updates to cross-disciplinary teams.
• Experience utilizing revision control systems for managing layout designs.

Preferred Skills and Competencies

• Knowledge or experience in optical or high-speed analog interface design is highly beneficial.
• Competency in scripting languages like SKILL, TCL, or Python to enhance automation and optimize design workflows.
• Demonstrated ability to collaborate effectively with teams based in the United States, Canada, and Argentina.
• Excellent organizational skills with great attention to detail and follow-through.
• Ability to juggle multiple priorities efficiently in dynamic, fast-paced environments.
• A proactive attitude, strong desire to learn, and robust problem-solving capabilities.

What We Provide

• An opportunity to be a founding contributor at a rapidly growing semiconductor startup.
• Engagement with diverse cross-functional teams.
• A collaborative and inclusive international culture that values initiative and ideas.
• Potential for professional growth as Celero expands and defines the future of AI and data center connectivity.