Principal Analog Design Engineer (SERDES)

About the Role

Join Cadence, a leading force in electronic design with over three decades of expertise in computational software. Our Intelligent System Design approach empowers us to create software, hardware, and IP solutions that transform design concepts into market-ready products. Our clients include the world's most forward-thinking innovators across diverse sectors such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health technologies.

We are seeking a Principal Analog Design Engineer specializing in SERDES to lead technical initiatives within our PMA design team based in Cork, Ireland. Reporting to the Design Engineering Group Director, this role demands expertise in high-speed data transmission technologies and leadership capabilities within circuit design and architecture.

Key Responsibilities

• Design high-speed SERDES systems supporting data rates of 112 Gbps and above, leveraging cutting-edge 5nm FinFET CMOS technology nodes.
• Develop and refine analog and mixed-signal integrated circuit blocks, steering projects from conceptual specifications through to final validation ensuring alignment with customer requirements.
• Collaborate closely with Physical Design Engineers to integrate IC circuit blocks and PMA modules seamlessly.
• Provide technical leadership within the team focusing on circuit design and SERDES architecture advancements.
• Coordinate effectively with global teams situated across different US time zones.

Candidate Qualifications

• A minimum of 7 years' experience designing and developing CMOS SERDES or other high-speed I/O integrated circuits.
• Educational background: Bachelor, Master, or Doctorate in Engineering or related field.
• Familiarity with standard SERDES specifications and their corresponding electrical performance requirements.
• Strong comprehension of jitter effects and signal equalization methods essential for signal integrity.
• Proven design experience in key SERDES components such as Drivers, Receivers, Serializers, Deserializers, Phase Interpolators, Low-jitter PLLs, High-speed Clock Distribution Networks, Bias and Bandgap References, and Voltage Regulators.
• Excellent analytical skills, strong analog design aptitude, effective communication, and a collaborative work style.

Preferred Skills

• Hands-on experience with Cadence design tools and working on projects exceeding 10 Gbps speeds.
• Lab testing and silicon evaluation exposure is a plus.
• Interest and experience in contributing to academic communities through publications and presentations at conferences such as ISSCC and JSSC.

Additional Information

Cadence is dedicated to fostering equal employment opportunities and embracing diversity at all organizational levels. We actively seek diverse talents and promote inclusive work environments.

Travel Requirement: Minimal, less than 5%.

We invite driven leaders and innovators eager to impact technology to join Cadence and tackle challenging problems others cannot solve.