LPU Chip Architecture Engineer

Role Overview

We seek an expert to lead the architectural design of LPU chips, focusing on static dataflow frameworks that address challenges like high latency and frequent data transfers during large-scale model inference. This role will involve spearheading computing array design, planning on-chip SRAM storage, and pioneering hardware-software collaboration with compiler teams to streamline scheduling logic before hardware fabrication. You will evaluate chip metrics such as compute throughput, bandwidth, and power use, benchmarking vs. traditional GPUs and NPUs. The position also includes iterative upgrades to support emerging multi-expert and multimodal large model inference requirements. Collaborating across design, prototype verification, and tape-out stages, along with competitive analysis of industry dataflow chips, will be key responsibilities.

Key Duties

• Define LPU chip architecture based on static dataflow and optimize compute array and on-chip SRAM hierarchy.
• Partner early with compiler engineers to co-develop hardware microarchitecture and pre-align scheduling logic to study hardware-software integration.
• Analyze and benchmark computing power, bandwidth, and energy consumption relative to GPU/NPU alternatives.
• Adapt and enhance architecture for next-generation large-scale MoE and multimodal inference applications.
• Engage in front-end chip design, FPGA prototyping, chip tape-out, and subsequent bring-up and performance tuning.
• Conduct competitive research on architectures from Groq, Etched, Cerebras; compile detailed analysis and recommendations.

Required Qualifications

• Master’s degree or higher in Microelectronics, Integrated Circuit, Computer Architecture, or related field with minimum 2 years AI chip architecture experience.
• Strong understanding of static dataflow and systolic array designs; knowledge of dual-stage Prefill and Decode inference concepts for large models. Experience with video memory and on-chip SRAM scheduling is a plus.
• Practical skills in AI chip, NPU, or GPU architecture design and front-end design flow, with proven hardware-software co-design competence.
• Proficient in evaluating chip performance through simulation and analysis covering compute, latency, and power consumption.

Preferred Skills and Experience

• Research and development background with dataflow or LPU chips.
• Experience tailoring hardware solutions for large model inference.
• Familiarity with AI compiler fundamentals.
• Advanced research experience on Groq chip architecture.