Lead Design Engineer

About the Role

Join Cadence as a Lead Design Engineer where you will contribute to cutting-edge technologies shaping the semiconductor industry. This position involves comprehensive responsibility for physical design implementation and verification on advanced nodes.

Key Responsibilities

• Take ownership of physical design processes including floor planning, power grid design, placement and routing, clock tree synthesis, timing and signal integrity closure, power and electromigration signoffs, physical verification encompassing DRC, LVS, antenna rules, and Design for Manufacturability (DFM) completion.
• Execute physical design implementation of Cadence intellectual properties using industry-standard EDA tools such as Genus, Innovus, Tempus, Voltus, and other backend utilities.
• Optimize design performance, power consumption, and area metrics for high-end interface IPs like DDR, LPDDR, PCIe, UCIe, and test chips targeting advanced semiconductor process nodes including 7nm, 5nm, 3nm, and 2nm.
• Engage with varied design challenges including low power, high speed, and area optimization tasks.
• Collaborate closely with RTL design and analog teams to guarantee timely and successful tapeouts.

Qualifications and Skills

• Minimum educational qualification: B.Tech, BE, ME, or M.Tech with 4 to 6 years of hands-on expertise in physical design and verification techniques.
• Comprehensive understanding of ASIC physical design flows, hierarchical strategies, and intricacies of deep sub-micron technologies.
• Proficient knowledge in physical design, static timing analysis, low power design methodologies, EM/IR and crosstalk analyses, formal and physical verification, as well as DFM and DFT considerations.
• Demonstrated success in tapeout of complex IPs and SoCs across process nodes 16nm down to 3nm with diverse foundries.
• Expert user of Cadence implementation tools including Genus, Innovus, Quantus, Tempus, PVS, and Voltus.
• Programming and automation skills with experience in Makefile, Tcl/Tk, Perl, Python, and familiarity with AI tools for design flow enhancements.
• Strong communication prowess, analytical thinking, problem-solving abilities, self-motivation, and effective teamwork.

Work Environment

This is an on-site, full-time role based in Pune/Pimpri-Chinchwad area, offering the chance to work on significant technological advancements in ASIC physical design.