Lead Analog Layout Design Engineer (SERDES/UCie)

About Cadence

Cadence is a leading force in electronic design with over three decades of experience in computational software. The company leverages its Intelligent System Design approach to deliver an integrated suite of software, hardware, and IP solutions that transform design concepts into practical electronic products. Cadence's clientele includes some of the world's most innovative companies, serving dynamic sectors such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and healthcare.

Role Overview

The Lead Analog Layout Design Engineer will assume a technical leadership position within the PMA custom layout team, focused on SERDES product development at Cadence Ireland located in Cork. Reporting to the Senior Principal Engineer, the role demands expertise in high-speed analog layout design for cutting-edge technology nodes.

Key Responsibilities

• Design high-speed SERDES interfaces for UCIe products supporting data rates up to 64 Gbps using advanced technology nodes such as 2nm FinFET CMOS.
• Create high-quality layouts of analog and mixed-signal circuit blocks in tight collaboration with circuit design teams.
• Manage all aspects of the backend physical design flow from initial floor planning through detailed layout and final verification ensuring compliance with foundry design rules.
• Lead and provide technical direction on layout design efforts ranging from individual blocks to PHY top-level integration and sign-off processes.
• Collaborate effectively with international teams across various time zones including the US west and east coasts.

Required Qualifications

• At least 7 years of professional experience in CMOS SERDES or high-speed I/O integrated circuit layout design and development.
• Proficient in layout design for multiple SERDES circuit components such as Driver, Receiver, Serializer, Deserializer, Phase Interpolator, Low Jitter PLL, High-Speed Clock Distribution, Bias and Bandgap circuits, and Voltage Regulators.
• Track record of implementing high-speed, high-accuracy cells and IP blocks with high quality and efficiency within project timelines.
• Experience collaborating globally with custom layout designers, circuit designers, and project managers to meet technical and scheduling requirements.
• Strong problem-solving abilities, solid analog engineering knowledge, excellent communication skills, and teamwork capability.
• Educational background including a Bachelor’s (BEng), Master’s (MEng), or PhD degree in a relevant engineering discipline.

Additional Skills and Preferences

• Experience using Cadence design tools with designs exceeding 10 Gbps data rates.
• Engagement with Cadence R&D teams such as Virtuoso and PVS developers to enhance layout editing and verification tools.
• Interest in pioneering evolutions in analog and custom layout design methodologies.

Additional Details

Cadence is dedicated to equal opportunity employment, emphasizing workforce diversity and inclusivity at all organizational levels. The position involves travel commitments exceeding 10% of the time. Join Cadence to contribute to cutting-edge technology challenges and create impactful solutions.