PERSOL APAC

Integrated Circuit Layout Design Engineer

PERSOL APAC

Singapore · Full Time

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Experience
3–4 yrs
Salary
Openings
1
Posted
1 day ago
Work mode
In office
Education
Bachelor's degree in Electronic and Electrical Engineering or Microelectronics
Resume
Required to apply

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Job description

Company Overview

Our client is a globally recognized leader in information and communications technology (ICT) infrastructure and smart devices. They provide comprehensive full-stack, all-scenario solutions serving carriers, enterprises, governments, and individual consumers worldwide.

Role Overview and Responsibilities

  • Create and deliver physical design verification clean layouts for mixed signal and analog circuits, using deep submicron CMOS technologies.
  • Collaborate with circuit designers to review and analyze floor plans and complex circuits to guarantee accurate integration.
  • Execute thorough design verification processes on circuit blocks ensuring correctness and compliance with specifications.
  • Work jointly with circuit design teams to troubleshoot and resolve intricate technical problems.
  • Enhance layout workflows to promote faster and higher quality design output.
  • Partner closely with circuit designers to surpass engineering specifications and meet performance objectives.
  • Utilize advanced CAD tools and mask design expertise to produce robust layouts satisfying strict criteria for matching, performance, area, and power consumption.

Candidate Qualifications

  • Bachelor's degree in Electronic and Electrical Engineering, Microelectronics, or a closely related field.
  • 3 to 4 years of proven experience in analog layout design covering components such as RFs, SerDes, ADCs, DACs, LDOs, PLLs, bandgap references, and amplifiers.
  • A minimum of 3 years experience with layout and top-level IC integration within CMOS technologies including 28nm, 16nm, and 7nm nodes.
  • Strong skills in custom and standard-cell floor planning and hierarchical layout creation.
  • In-depth knowledge of critical layout aspects such as IR drop, RC delay, electro-migration, self-heating, and cross-capacitance phenomena.
  • Proven ability to identify circuits and layout features prone to failure; familiar with analog and design-for-manufacturing (DFM) standards.
  • High competency interpreting CALIBRE DRC, ERC, LVS reports and resolving related issues.
  • Expertise in layout tools such as MENTOR GRAPHICS or CADENCE.
  • Additional scripting capabilities in Perl, Python, or SKILL are advantageous.
  • Excellent interpersonal and communication skills facilitating collaborative teamwork across functions.

Additional Information

Interested applicants are encouraged to apply for this position. Kindly note that only candidates shortlisted will be contacted.

EA License No.: 01C4394

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Minimum education

Bachelor's Degree

Tools & software

Mentor Graphics required

How they work

Communication Teamwork & Collaboration Problem Solving Attention to Detail
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