FPGA Development Tools Engineer – Synthesis

Overview

Altera leads in FPGA innovation, providing programmable solutions essential for AI, cloud computing, networking, and edge applications. Our FPGA compiler and development tools empower customers to design, optimize, and deploy sophisticated hardware systems efficiently on cutting-edge FPGA platforms.

Position Summary

We are seeking an FPGA Development Tools Engineer specializing in the Synthesis domain to help shape the next generation of FPGA compilation technology. You will focus on enhancing synthesis features that convert RTL designs into optimized gate-level implementations, improving performance, power consumption, and area footprint.

Key Responsibilities

• Design, develop, and refine synthesis algorithms that transform RTL code (Verilog, SystemVerilog, VHDL) into optimized gate-level hardware representations.
• Participate in the FPGA compiler toolchain by integrating synthesis processes with placement, routing, and static timing analysis phases.
• Enhance quality of results (QoR) by applying synthesis-driven techniques targeting improved performance, power efficiency, and area utilization.
• Create and apply methodologies and tools for analyzing and manipulating complex RTL structures.
• Collaborate cross-functionally with architecture, timing analysis, placement, routing, and validation teams to ensure seamless toolchain operations.
• Investigate synthesis outputs, identify issues related to timing, logic, or mapping, and spearhead their resolution.
• Develop internal scripting tools and automation processes to streamline synthesis workflows and increase productivity.

Compensation

We offer competitive salaries aligned with the Canadian job market, ranging approximately from CAD 129,100 to CAD 187,000 annually depending on location, experience, skills, and expertise. Performance-related incentives are also available to reward individual and company-wide success.

Candidate Qualifications

• Minimum of 6 years' experience in FPGA or ASIC design, or EDA tool development.
• Strong practical experience with RTL design and synthesis flows using Verilog, SystemVerilog, or VHDL languages.
• Proficient in C/C++ programming for developing synthesis tools.
• Deep understanding of algorithms, data structures, debugging techniques, and performance evaluation.
• Familiarity with logic synthesis, optimization methods, and complete FPGA/ASIC design flows including placement, routing, and static timing analysis.
• Ability to solve complex problems and develop scalable, efficient solutions.
• Educational background includes a Bachelor’s, Master's, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or related disciplines.

Preferred Experience

• Hands-on experience with synthesis or FPGA toolchains such as Quartus or Vivado.
• Knowledge of FPGA architectures including LUTs, DSP blocks, BRAM, and interconnects.
• Experience with advanced synthesis optimizations like retiming, logic restructuring, and resource sharing.
• Familiarity with scripting languages like Python or Tcl for automation.
• Background in compiler construction or EDA algorithm design.
• Ability to work effectively within large, geographically distributed engineering teams.

Why Work With Us

• Contribute to building foundational synthesis technology for cutting-edge FPGA platforms.
• Impact the architecture and performance of FPGA compilers on a large scale.
• Collaborate alongside top engineers across silicon design, architecture, and software development.

Additional Information

Employment is based in Toronto, Ontario, Canada. We provide equal opportunity in employment without discrimination based on any protected category. Candidates must satisfy any Canadian export authorization requirements. Canadian work experience is not mandatory. Artificial Intelligence techniques are used in the candidate screening process.