Engineer II, Layout Design

About SiTime

SiTime is recognized as a leader in Precision Timing technology. Precision timing is fundamental to electronics for ensuring performance, resilience, and scalability. Traditional quartz devices have been used for decades but are less suitable in demanding environments. SiTime’s MEMS-based timing solutions deliver enhanced accuracy, smaller footprint, and improved durability, powering over 400 diverse applications such as AI datacenters, autonomous vehicles, industrial and humanoid robotics, wearables, and IoT devices.

SiTime’s semiconductor MEMS programmable products provide a robust feature set, helping customers build products with superior performance, smaller size, lower energy consumption, and greater reliability. With over 4 billion units shipped, SiTime is reshaping the timing industry.

Role Overview

The Engineer II in Layout Design will lead block-level chip planning and execute custom analog layout design for CMOS and BiCMOS technologies. Responsibilities include managing offshore layout teams, training junior engineers and contractors, advancing layout methodologies, and implementing processes that uphold high design quality.

Key Responsibilities

• Collaborate virtually with design and layout teams across multiple global sites and time zones.
• Lead and execute custom analog layout design on various levels including functional blocks, sub-blocks, leaf cells, and standard cells for CMOS and BiCMOS circuitry.
• Create schematic-driven layouts that observe design requirements and constraints.
• Develop compact, functionally compliant block layouts.
• Design block-level floorplans, power distribution schemes, shielding, and matched device layouts.
• Perform verification processes ensuring DRC, LVS, and ERC signoff success.
• Support chip-level routing and related layout operations.
• Assist in chip integration, verification, and tape-out milestones.
• Provide training and mentorship to junior engineers and offshore contractors.
• Facilitate the establishment and continuous improvement of layout methodologies, best practices, and workflows across sites.
• Help shape procedures aimed at achieving exceptional layout quality.

Qualifications and Experience

• Bachelor’s degree or equivalent experience in Layout Design or related discipline.
• Minimum 5 years of proven experience in analog and full-custom digital layout design.
• Hands-on experience with process technologies such as TSMC 180nm, 65nm, and 22nm.
• Proficiency in Cadence Virtuoso for layout editing.
• Strong knowledge of design rule check (DRC), layout versus schematic (LVS), and electrical rule check (ERC) debugging tools like Cadence PVS or Mentor Calibre.
• Comprehensive understanding of layout-related aspects including parasitics, device matching, crosstalk, latch-up, electromigration, IR drop, and isolation techniques.
• Skilled at resolving challenges in device matching, electromigration, signal integrity, and power distribution within tight area constraints.
• Experience with chip-level floorplanning, analog block integration, verification, and tape-out processes.
• Adept at leveraging productivity tools and scripting to automate layout workflows.
• Ability to physically lift or move up to 5 pounds.

Desired Personal Attributes

• Exceptional attention to detail, organization, and accuracy.
• Demonstrated ability to deliver work within project timelines.
• Self-driven team player who communicates effectively.
• Capability to thrive in a dynamic, fast-paced collaborative environment.

Compensation and Equal Opportunity

The compensation package is highly competitive, including base salary, quarterly performance bonuses linked to innovation goals, and equity ownership options reflecting commitment to recognize impactful contributions.

SiTime is an equal opportunity employer committed to an inclusive workforce free from discrimination or harassment based on protected characteristics. The company participates in the E-Verify program.