Director, Silicon Logical Design

About Graphcore

Graphcore is pioneering the next generation of AI computing by integrating expertise across semiconductors, software, and data center infrastructure. Backed by SoftBank Group's substantial investment, the company delivers groundbreaking technologies into a rapidly expanding AI ecosystem.

We aim to recruit visionary professionals to collaborate on solving challenging problems and to contribute significantly to our products and the future field of artificial intelligence.

Position Summary

The role of Director of Silicon Logical Design involves leading and expanding the Logical Design team within the Silicon department. The individual will set the strategic vision and technical roadmap, ensuring that microarchitecture and RTL implementations meet exceptional standards in performance, power efficiency, chip area, and timing. This position requires close partnership with Architecture, Physical Design, Verification, Design for Test, and Program Management to guarantee predictable silicon delivery aligned with long-term product objectives.

Team and Responsibilities

• Lead a multi-location Logical Design group responsible for micro-architecture and RTL delivery, strengthening collaboration across functions.
• Define and execute strategic plans in harmony with Graphcore's silicon and product strategies.
• Mentor and develop a high-performing team specializing in RTL and micro-architecture design.
• Implement industry-leading design methodologies, documentation, and quality assurance metrics.
• Continuously enhance team structures, workflows, tooling, and processes.
• Provide technical supervision over micro-architecture definitions and RTL development for all major blocks and subsystems.
• Drive architectural feasibility evaluations, trade-off discussions, and define micro-architectural details.
• Manage integration of third-party intellectual property, application-specific blocks, and custom high-performance designs.
• Ensure thorough design verification through linting, synthesis, CDC/RDC checks, timing closure, and coverage analysis.
• Collaborate closely with Physical Design, Verification, DFT, Architecture, and Program Management to synchronize planning and delivery efforts.
• Promote effective communication across global sites, ensuring alignment on priorities, risks, and milestones.
• Support silicon bring-up and debug with expert guidance on RTL behavior and architectural considerations.
• Manage delivery of high-quality RTL across several concurrent silicon projects, adhering to schedules.
• Implement structured project planning, resource allocation, and risk mitigation strategies.
• Advocate for design automation and infrastructure enhancements to boost productivity and quality.

Qualifications and Experience

• Degree in Computer Science, Electrical Engineering, or related discipline; advanced degrees preferred.
• Extensive background in digital logic design, micro-architecture, and RTL development for complex, high-performance silicon chips.
• Proven track record in leading and nurturing semiconductor design teams.
• Expertise in SystemVerilog or VHDL and modern digital design methodologies.
• Strong problem-solving skills including scripting/programming experience (Python, Tcl, etc.) to address design challenges.
• Excellent leadership and communication skills facilitating collaboration across geographically distributed teams.
• Robust organizational capabilities to handle multiple priorities and execute effectively in fast-paced settings.

Preferred Experience

• Knowledge of processor or accelerator microarchitecture.
• Experience with high-speed serial interfaces and complex, high-bandwidth IP blocks.
• Familiarity with arithmetic pipeline design and floating-point datapaths.
• Advanced proficiency in synthesis, timing and power analysis, logical equivalence checking.
• Expertise in design-for-test techniques.
• Understanding of power integrity and silicon device physics.
• Experience with silicon bring-up and post-silicon validation processes.
• Leadership experience in program planning and managing multiple concurrent projects.