AMS, RF, Memory, and Standard Cell Layout Engineer with Experience in Advanced Technology Nodes

Role Overview

This position involves taking independent responsibility for the physical design and layout of high-performance analog integrated circuit blocks, including ADCs, DACs, PLLs, and SERDES. Success in the role is measured by the ability to create layouts that ensure optimal device performance and reliability across advanced technology nodes ranging from 90nm down to 3nm.

Key Responsibilities

• Independently perform IC layout of complex analog blocks such as ADC, DAC, PLL, and SERDES, ensuring adherence to stringent performance and quality standards.
• Identify and mitigate layout-dependent effects that can impact circuit functionality and robustness.
• Generate layouts compliant with physical verification checks including Design Rule Checks (DRC), Layout Versus Schematic (LVS), Design for Manufacturability (DFM), Electrical Rule Check (ERC), Electromigration (EM), and IR drop analysis.
• Develop automation scripts and tools using programming languages like SKILL, PERL, or Python to streamline layout tasks and improve productivity.
• Exhibit self-motivation to define work schedules and layout methodologies to meet project timelines effectively.
• Collaborate effectively within a team environment, demonstrating excellent interpersonal and communication skills.

Required Qualifications

Applicants must hold a Bachelor of Engineering (B.E.) or Bachelor of Technology (B.Tech) degree in Electronics and Communication Engineering or an equivalent field.