Staff NPU STA/Timing Engineer

About the Company

Qualcomm India Private Limited is a renowned technology leader committed to pushing the limits of innovation to enable next-generation experiences and advance digital transformation for a connected smarter future. The Engineering Group, specifically Hardware Engineering, focuses on developing cutting-edge electronic and digital systems.

Role Overview

The Staff NPU STA/Timing Engineer will be involved in planning, designing, optimizing, verifying, and testing various electronic systems including circuits, equipment, packaging, Digital/Analog/RF/optical systems, FPGA, and DSP systems. This role demands collaboration across multiple teams and adherence to performance specifications.

Primary Responsibilities

• Set up, converge, review, and approve static timing analysis (STA) for complex multi-mode, multi-voltage domain designs.
• Conduct timing analysis, validation, and debugging over multiple process-voltage-temperature (PVT) corners using PrimeTime (PT) or Tempus tools.
• Execute STA flow optimizations and correlate Spice simulations to STA results.
• Assess different timing methodologies and tools across diverse designs and technology nodes.
• Develop and enhance automation scripts within STA and Physical Design (PD) tools to refine methodologies.
• Write technical documentation clearly and work effectively in cross-functional environments.
• Engage in design automation using scripting languages like TCL, Perl, and Python.
• Familiar with full digital design flow from RTL to GDS using ICC, Innovus, PT, and Tempus.
• Support process technology enablement including circuit simulations with Hspice/FineSim and Monte Carlo techniques.

Qualifications and Experience

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related discipline with at least 2 years of hardware engineering experience; OR
• Master's degree with at least 1 year of relevant experience; OR
• PhD in a related field.

Preferred Skills

• Between 5 to 10 years of dedicated experience in STA and timing analysis.
• Strong knowledge in STA fundamentals including AOCV/POCV concepts, clock tree synthesis (CTS), timing constraints management, latch transparency, zero and multi-cycle paths handling.
• Hands-on proficiency with PrimeTime and Tempus STA tools.
• Demonstrated experience driving timing closure at both chip and hard-macro levels.
• Comprehensive understanding of cross-talk noise, signal integrity, layout parasitic extraction, and feed-through considerations.
• Familiarity with ASIC backend design flows, tools like ICC2 and Innovus.
• Expertise in Spice simulation tools such as Hspice, FineSim, Monte Carlo, and correlating silicon to Spice models.
• Proficiency in scripting languages including TCL, Perl, and AWK.
• Basic comprehension of semiconductor device physics.

Additional Information

Qualcomm is an equal opportunity employer committed to accessibility and accommodations for individuals with disabilities throughout the hiring process. Reasonable accommodations will be provided upon request. Applicants are expected to comply with company policies concerning confidentiality and information protection.

Third-party recruiters and staffing agencies are not authorized to submit applications through this platform; unsolicited resumes will not be accepted.