Staff Engineer - HBM Layout Design

About Micron Technology

Micron Technology has been a pioneering force in memory and storage innovation for over 45 years, accelerating how information transforms into intelligence to enhance lives globally. With expertise in memory and semiconductor technologies, the company fosters a dynamic international environment of visionaries dedicated to advancing AI, 5G, and computing.

Role Overview

We are seeking a skilled Layout Design Engineer to join the High Bandwidth Memory (HBM) team in Hyderabad, India. This role involves crafting layouts for complex applications such as artificial intelligence and high-performance computing. The engineer will collaborate across Micron's global sites, managing multiple projects simultaneously.

Key Responsibilities

• Design and develop critical components including mixed-signal and custom digital blocks and provide support for full chip-level integration.
• Develop and tape out PWF Reticles designs, integrating advanced packaging needs.
• Coordinate with Scribe Design teams to incorporate packaging requirements.
• Collaborate with HBM DTPCO teams on Through-Silicon Via (TSV) design, focusing on electrical, thermal, and mechanical performance.
• Create and maintain Design Failure Mode and Effects Analysis (DFMEA) for advanced packaging processes including PWF and die stacking.
• Exercise a detail-oriented and systematic approach to IC layout design with a strong passion for precision.
• Conduct thorough layout verifications such as LVS, DRC, and Antenna checks, and ensure proper documentation.
• Deliver block-level layout designs punctually while maintaining quality standards.
• Lead project planning efforts including estimating area and time, scheduling, delegating, and executing across multiple projects.
• Mentor junior members by reviewing and guiding sub-block layout work.
• Contribute actively to project management and foster effective communication with global engineering teams to ensure project success.

Qualifications and Experience

• 8 to 15 years of experience in analog/custom layout design utilizing advanced CMOS process nodes (Planar and FinFET).
• Proficiency in Cadence VLE/VXL and Mentor Graphics Calibre DRC/LVS tools is essential.
• Hands-on experience designing layouts for critical circuit blocks including Temperature Sensors, PLL, ADC, DAC, LDO, Bandgap, Reference Generators, Charge Pumps, Current Mirrors, Comparators, and Differential Amplifiers.
• Expertise in reticle development and full-chip verification processes.
• Capability to leverage automation and AI tools for increased efficiency in project deliveries.
• Sound understanding of layout fundamentals including matching, electromigration, latch-up, coupling, crosstalk, IR-drop, and passive/active parasitic devices.
• Insight into how layout affects circuit parameters such as speed, capacitance, power consumption, and area.
• Strong problem-solving skills in custom layout physical verification, with experience supporting multiple tape outs considered advantageous.
• Experience managing various layout projects including quality assurance at every development phase.
• Excellent verbal and written communication skills.

Education

BE or MTech in Electronics or VLSI Engineering.

Additional Information

We are committed to equal employment opportunities regardless of race, color, religion, gender or veteran status. Candidates are encouraged to apply and should ensure that all application details truthfully represent their skills and experience. Our hiring process prohibits child labor and any form of recruitment fees.

For applicants needing reasonable accommodation or assistance with the application, contact support is available.

Note on Artificial Intelligence Usage: Applicants may use AI tools to improve resumes or applications; however, all submitted information must be honest and authentic. Misrepresentation will lead to disqualification.

Fraud Alert: Beware of fraudulent job offers. Always verify communications through our official channels.