STA Engineer

Role Overview

We are seeking an experienced STA Engineer based in Bangalore with 5 to 6 years of relevant expertise. The ideal candidate will have in-depth knowledge of subsystem or full-chip level Static Timing Analysis (STA) closure, utilizing advanced tools and methodologies to achieve timing sign-off efficiently at scale.

Key Responsibilities

• Manage and execute STA closure for subsystems and full-chip designs.
• Develop and apply constraint hacks and perform rigorous validation to meet timing requirements.
• Use industry-standard tools such as PrimeTime (PT), PrimeClosure, Tempus, and Tweaker for performing timing analysis and closure tasks.
• Handle flat level and subsystem Engineering Change Order (ECO) rolling processes.
• Concentrate efforts on post-layout STA activities, excluding pre-layout STA or combined Place and Route (PnR) and STA roles.

Candidate Profile

• Strong background and proven skills in VLSI/ASIC STA methodologies.
• Ability to tackle complex timing challenges particularly in advanced semiconductor technology nodes.
• Excellent problem-solving capability with a focus on debugging and resolving timing issues effectively.