Server Structural FEA Engineer

About Qualcomm Data Center Engineering

Qualcomm Technologies, Inc. is pioneering the creation of high-performance and energy-efficient server platforms tailored for data center use. The team is dedicated to revolutionizing computing platforms through cutting-edge silicon design and comprehensive hardware-software integrations. This role operates within the systems engineering group focused on reference platforms leveraging Qualcomm Snapdragon SoCs.

Role Overview

We are recruiting a highly experienced Staff or Senior Staff Server Structural Finite Element Analysis (FEA) Engineer with advanced expertise in packaging mechanics, structural reliability, and finite element modeling for semiconductor servers. The position centers on ensuring the structural integrity of server system-on-chips (SoCs) at the die and package level, including their mechanical interplay with the encompassing platform components such as PCBs, sockets, and thermal management systems.

Key Duties

• Develop and implement advanced FEA models addressing structural and thermo-mechanical phenomena for server SoCs and semiconductor packaging, focusing on issues like chip-package interaction, warpage, and structural stress.
• Assess mechanical performance under varied conditions including assembly, surface mount technology processes, socket retention forces, cooling system loads, thermal cycling, qualification, and runtime environments.
• Simulate the mechanical dynamics between the SoC package and platform elements such as PCBs, sockets, thermal interface materials (including TIM1.5), heatsinks, and cold plates.
• Utilize sophisticated FEA techniques: submodeling, contact mechanics, nonlinear material behavior, viscoelasticity, creep phenomena, fatigue analysis, fracture mechanics, and integrated structural-thermal simulations.
• Formulate physics-based models for reliability and life expectancy predictions addressing failure causes including solder and bump fatigue, stress on die and back end of line (BEOL), substrate and interposer cracking, delamination, and creep damage.
• Conduct sensitivity and uncertainty analyses to prioritize impact factors, evaluate structural risks, and inform design decisions ahead of hardware fabrication.
• Design and execute model validation plans aligning with physical tests, reliability data, manufacturing insights, and system-level examinations.
• Coordinate closely with engineering groups in package design, computational modeling, thermal, mechanical, electrical, manufacturing, reliability, and system levels to establish consistent modeling assumptions and parameters.
• Independently perform targeted verification analyses and collaborate with system structural engineers to map package behaviors to platform-wide mechanical assessments throughout the product lifecycle.
• Apply domain knowledge of advanced packaging technologies including but not limited to FCBGA, FCLGA/HFCBGA, chiplet architectures, HBM integration, 2.5D interposers/bridges, and 3D packaging.
• Develop scalable and automated workflows, modeling standards, and validation processes ensuring model repeatability and quality; prior experience with ANSYS APDL scripting is preferred.
• Convert complex simulation outputs into clear, actionable recommendations suitable for cross-functional teams, management, customers, and supply chain partners.

Required Qualifications

• Master’s degree in Mechanical Engineering, Engineering Mechanics, Materials Science, Physics, or a related discipline.
• At least 10 years of progressive experience in finite element analysis focusing on semiconductor packaging, microelectronic assembly, and reliability engineering.
• Solid understanding of structural mechanics, failure analysis, materials science, thermal and mechanical behaviors including fatigue and creep, with demonstrated nonlinear FEA applications.
• Proven competency in modeling semiconductor package failure and correlating simulation results with empirical and qualification data.
• Proficiency with leading FEA software such as ANSYS Workbench, ANSYS APDL, or ABAQUS.
• Strong independent working capability combined with leadership in multidisciplinary team settings, excellent communication, documentation, and presentation skills.

Preferred Qualifications

• Ph.D. in Mechanical Engineering or related fields.
• Extensive knowledge of package mechanics, chip-package interaction, warpage, and interconnect reliability.
• Experience with both soldered and socketed high pin-count server packages and related platform component interactions.
• Development of analytical reliability models and life predictions for solder joints, package substrates, interposers, underfills, and adhesives.
• History of successfully correlating simulation data with warpage, strain, displacement experiments, and thermal-mechanical qualification testing.
• Experience automating APDL workflows, implementing best practices, and standards in FEA modeling.
• Expertise in coupled structural-thermal analyses and mechanical-thermal optimization strategies.
• Good understanding of server/OCP platform design, assembly processes, and qualification environment conditions.

Additional Information

Qualcomm promotes equal opportunity employment and provides reasonable accommodations for candidates with disabilities upon request. The company strictly prohibits submissions from recruiting agencies through their formal job application platform. Employees are expected to adhere to confidentiality and security policies. The salary range for this role is $190,200 to $285,400 per year, supplemented by a discretionary annual bonus program, RSU grants (excluding sales incentive employees), and a comprehensive benefits package supporting work-life balance.