Senior Sensors Design Verification Engineer

About the Role

Join Qualcomm, a trailblazer in technology innovation committed to advancing next-generation communication and data processing. This role involves active participation in various sensor system engineering tasks within the Sensors Technologies division.

Key Responsibilities

• Implement state-of-the-art verification techniques including UVM and Formal Verification.
• Create comprehensive testbenches and verification assets such as UVCs, C model integrations, and reusable horizontal and vertical verification frameworks.
• Ensure the validity of sensor algorithm RTL for ASIC tapeout readiness through meticulous verification.
• Develop test plans guided by design documentation and engage closely with design and system engineering teams.
• Integrate C models into the UVM verification environment.
• Write SystemVerilog assertions to reinforce verification coverage.
• Perform debugging, verification optimization, and achieve bit-accurate matching to test vectors.
• Analyze coverage statistics and collaborate with design teams to mitigate coverage gaps.
• Enhance frameworks for regression test automation and manage regression failure investigations alongside design and systems teams.
• Support subsystem-level integration with test plan formulation, test vector management, and debugging at the subsystem integration stage.
• Develop Python scripts to automate workflows and improve team efficiency.
• Participate actively in all stages of project review cycles.
• Provide debugging assistance to software and other cross-functional teams.
• Maintain thorough documentation of all verification activities.

Qualifications and Experience

• A Bachelor's degree in Science, Engineering, or a related discipline is required.
• Minimum of 4 years experience in ASIC design verification or functional verification utilizing UVM methodologies.
• Familiarity with formal verification tools such as Jasper or VC_Formal is advantageous.
• Experience with SystemC and Matlab software is beneficial.
• Knowledge of gate level simulation debug and power extraction tools is a plus.
• Proficient in building constrained-random verification environments using UVM and employing coverage-driven verification techniques.
• Experienced in writing and utilizing SystemVerilog Assertions for verification.
• Skilled at debugging test failures and reporting verification outcomes to meet expected code, functional, and line coverage benchmarks.
• Extensive use of RTL simulation tools.
• Competent with UVM, SystemVerilog, and scripting languages such as Perl and Python.
• Basic understanding of C/C++ programming.
• Strong analytical abilities; able to thrive in dynamic, fast-paced teams.
• Excellent written and verbal communication skills.
• Good interpersonal skills and ability to contribute positively to a team environment.

Work Location

This position is based in Cork, Ireland — a vibrant economic hub housing over 170 international companies and a culturally diverse population. The region offers a high quality of life and international connectivity via Cork Airport.

Equal Opportunity Employment

The employer practices equal opportunity hiring, welcoming all qualified candidates regardless of race, color, religion, sexual orientation, gender identity, national origin, disability, veteran status, or other protected categories.

Benefits and Perks

• Competitive salary with stock options and performance-linked bonuses.
• Paid maternity and paternity leave.
• Participation in employee stock purchase plan.
• Company-matched pension contributions.
• Educational support programs.
• Assistance with relocation and immigration where applicable.
• Comprehensive insurance coverage including life, medical, income, and travel insurance.
• Subsidies for physical and mental wellness activities.
• Scheme for bicycle purchases.
• Access to employee-run clubs offering activities such as running, football, chess, badminton, among others.

Additional Information

• Qualification pathways: Bachelor’s degree with 2+ years, Master’s degree with 1+ year, or PhD in relevant fields with comparable experience are accepted.
• Experience year requirements are indicative; equivalent experience with capability to perform role responsibilities is considered.
• Commitment to workplace accessibility and accommodation for individuals with disabilities.
• Employees must adhere to all company policies concerning protection of confidential and proprietary information.
• Recruitment agencies should note that unsolicited resumes are not accepted.