Senior Engineer - EDA Flow and Logic Synthesis

Overview

Synopsys is a technology leader driving innovations in chip design, verification, and IP integration crucial to advanced intelligent systems such as self-driving cars and learning machines. Within the HPC Controller IP team, the mid-end group operates as the crucial link between RTL design and physical implementation. This team creates the workflows, automation tools, and quality controls necessary to synthesize, verify, package, and release advanced soft IP efficiently, delivering clean and implementation-ready inputs to physical design teams.

Key Responsibilities

• Create, execute, and maintain mid-end workflows covering synthesis, Design-for-Test (DFT), static check tools like SpyGlass, formal equivalence, and power analysis alongside other quality assurance gates.
• Translate RTL outputs into constrained, implementation-ready inputs suitable for physical design teams.
• Develop and sustain automation and project infrastructure using Tcl scripting; leverage AI capabilities to accelerate tasks such as log analysis, result summarization, and script generation/refinement.
• Investigate flow failures comprehensively by analyzing reports, locating root causes, and collaborating with design, verification, DFT, and implementation teams to resolve issues.
• Enhance documentation, handoff standards, and reusable assets to ensure consistency across IP development programs.

Impact Delivered

• Improve the quality and reliability of RTL to physical design handoffs, lowering implementation risks.
• Accelerate and scale workflows through enhanced automation and AI-assisted analysis.
• Identify synthesis, DFT, static checks, formal, and power-related problems earlier in development.
• Boost cooperation across RTL and implementation teams for seamless integration.
• Guarantee robust, ready-to-implement soft IP packages with precise constraints and comprehensive release materials.

Required Qualifications

• At least two years of practical experience or equivalent project involvement with ASIC design, verification, and mid-end flow development.
• Demonstrable hands-on experience in synthesis with proficiency in diagnosing and solving related issues.
• Strong Tcl scripting abilities alongside a pragmatic, automation-first approach.
• Familiarity with DFT concepts, static checking tools like SpyGlass, formal equivalence tools such as Formality, and power analysis methodologies, with a willingness to expand expertise.
• Experience applying AI tools effectively to streamline debugging, consolidate quality metrics, and optimize scripts and flows.
• Excellent analytical thinking, problem-solving aptitude, clear communication, and documentation skills.
• Bachelor’s or Master’s degree in Electrical or Computer Engineering, or equivalent practical experience.

Preferred Skills

• Experience spanning the full mid-end toolset: DFT, SpyGlass, Formality, and power analysis.
• Knowledge of IP development methods, packaging, and delivery processes for reusable IP.
• Familiarity with Synopsys tools such as Fusion Compiler and VC SpyGlass is advantageous.

Personal Attributes

• Proactive, curious, and able to adapt to changing environments.
• Collaborative with strong ethical standards.
• Focused on quality, process-driven, and familiar with AI integration in workflows.
• Resilient and determined to achieve results.

Team Environment

The role will be part of a high-impact High-Performance Compute team delivering complex IP for a competitive market. The position collaborates closely across multiple disciplines including RTL design, verification, DFT, physical design, methodology, and project infrastructure to ensure mid-end readiness and facilitate reliable downstream implementation.

Compensation and Benefits

Synopsys offers a comprehensive suite of health, wellness, and financial benefits tailored to employee needs. Specific salary and benefits details are communicated during the recruitment process.