Senior Design Verification Engineer

About the Opportunity

Blue Fish Technologies is seeking a Senior Design Verification Engineer specialized in UVM ASIC projects, based in Hyderabad, India. The ideal candidate holds a B.Tech or M.Tech in Electronics & Communication Engineering and has at least 5 years of experience in complex ASIC verification cycles from test planning through tapeout.

Key Responsibilities

• Lead the functional verification efforts of a cutting-edge mixed-signal Sensor ASIC.
• Collaborate closely with design and architecture teams to understand and validate functionality at block, chip, and system levels.
• Create and implement detailed test plans covering directed and constrained-random testing methods.
• Develop and analyze functional coverage metrics to iteratively enhance verification performance.
• Provide expert technical guidance and foster innovative approaches to improve quality, verification processes, and productivity.

Candidate Profile and Requirements

• Minimum 5 years experience working with complex ASIC design verification projects.
• Demonstrated proficiency in SystemVerilog and UVM methodology, including UVM testbench development and reusable verification components (UVCs).
• Strong object-oriented programming skills, with solid understanding of computer architecture and data structures.
• Experience in AMS design verification is advantageous.
• A track record of advancing process and methodology to boost verification quality and productivity.
• Knowledge working on Ethernet, SERDES, MAC, PCS, SPI protocols and associated VIPs.
• Familiarity with Python scripting and Makefile build systems.