Senior ASIC Design Verification Engineer

About Ethernovia

Ethernovia is pioneering the future of Ethernet-based networking to unlock the potential of software-defined autonomous vehicles, robotics, and other intelligent machines. Founded in 2018, the company’s innovative data transport and acceleration technologies are enabling unprecedented connectivity and capabilities at the edge, including highly reliable autonomy, over-the-air updates, and AI-driven applications.

Supported by leading technology investors with over $154 million in funding to date, Ethernovia has been recognized among EE Times' Top 100 Startups for 2025 and collaborates with major players like Porsche SE, Qualcomm, and Continental. With a global team and over 50 patents filed, Ethernovia is driving the next generation of packet processor-centric networking solutions for real-time sensors and control data in vehicles, robots, and intelligent machines.

Position Overview

We are seeking a Senior ASIC Design Verification Engineer to oversee all facets of digital SoC verification. This role involves close collaboration with architects, designers, and software engineers to plan and execute verification and validation of advanced automotive communication semiconductors and systems. The role supports remote work from Canada with a future hybrid work option in the Toronto/Markham area.

Key Responsibilities

• Lead verification activities for digital ASIC SoCs, ensuring thorough coverage and validation.
• Collaborate with cross-disciplinary teams including architects, design, and software to create verification plans.
• Analyze simulation failures to diagnose and resolve root causes.
• Contribute positively to a culture founded on integrity, trust, and strong work ethics.

Required Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or related field.
• At least 10 years of hands-on experience in ASIC verification.
• Solid knowledge of ASIC verification fundamentals and familiarity with industry-standard methodologies.
• Proficient with Verilog/SystemVerilog, UVM, Python, TCL, and C/C++.
• Experienced with the complete verification process—from specifications through coverage analysis to gate-level simulation.
• Ability to independently debug and resolve simulation issues effectively.
• Self-driven and capable of working well both autonomously and within a team environment.

Additional Desired Expertise

• Experience in networking domains such as Ethernet MAC, PHY, switching, TCP/IP, security, PCIe, and other standard protocols.
• Familiarity with video standards, protocols, and processing techniques.
• Knowledge of digital signal processing filters.
• Experience working with third-party IPs like SerDes, controllers, and processors.
• Competence in developing modular and reusable verification testbench architectures.
• Designing tests and infrastructure for reuse in both pre- and post-silicon phases.
• Automation skills in testbench generation, regression testing, or EDA tool workflows.
• Understanding of SystemC and/or DPI interfaces.

Personal Attributes

• Strong communication and documentation capabilities.
• High attention to detail.
• Ability to collaborate effectively with multidisciplinary, international teams.

Employee Benefits and Opportunities

• Exposure to deep technology challenges unmatched by larger firms.
• Career advancement aligned with company growth.
• Pre-IPO stock option opportunities.
• Work with cutting-edge technology and a world-class team.
• Competitive salary package with flexible working hours.
• Comprehensive medical, dental, and vision insurance coverage.