Principal Verification Engineer

Job Overview and Location

This role is based in Hyderabad, Telangana, India and requires 9 to 15 years of industry experience in verification engineering.

Verification Planning and Execution

• Create detailed verification strategies and plans grounded in architectural and design specifics.
• Develop verification environments spanning block, subsystem, and SoC levels.
• Drive verification completion by monitoring functional, code, assertion, and toggle coverage metrics.
• Formulate test plans, verification test cases, and establish criteria for sign-off.

Testbench Development

• Design scalable verification environments using SystemVerilog and UVM methodologies.
• Implement reusable components such as UVCs, scoreboards, checkers, monitors, and reference models.
• Create tests that are constrained-random, directed, and scenario-based for comprehensive coverage.
• Integrate both third-party and proprietary verification IPs effectively.

Assertion and Formal Verification

• Write SystemVerilog Assertions (SVA) to check protocols and functional behavior.
• Apply assertion-based verification techniques aimed at enhancing bug detection rates.
• Collaborate with formal verification teams to develop properties and achieve closure.

Debug and Root Cause Analysis

• Analyze simulation failures to pinpoint issues related to RTL, testbench, or architectural design.
• Coordinate with design and architecture teams to resolve bugs affecting functionality and performance.
• Lead complex debugging efforts involving multiple IPs and subsystems.

Coverage and Sign-Off

• Define functional coverage models and monitor their progress.
• Manage closure on functional, code, assertion, and cross-coverage metrics.
• Review verification data and provide recommendations for sign-off.
• Ensure adherence to overall project verification goals and quality standards.

SoC Verification

• Lead comprehensive end-to-end verification of large SoCs covering:
• Interconnect and fabric verification
• Cache coherency validation
• Memory subsystem verification
• Boot and reset validation processes
• Low-power mode verification
• Performance and stress testing

Leadership and Mentorship

• Guide verification teams with technical leadership.
• Mentor both junior and senior engineers in UVM, methodologies, and debugging.
• Engage in hiring, technical interviewing, and project planning activities.
• Promote best practices and enhance verification processes continuously.

Contact

For further inquiries, contact: srinivas.kota@nxp.com