Principal Engineer - Digital Design

About Microchip Technology Inc.

Join a global leader with over 17,000 employees dedicated to creating technology that powers the modern world. Microchip fosters an inclusive culture of trust, respect, empowerment, and diversity, priding itself on supporting employee development through nationally recognized Leadership Passage Programs that benefit over a thousand individuals annually. The company’s commitment to values-driven decision making and community engagement has earned numerous diversity and workplace excellence accolades. As a financially successful enterprise with a 30-year streak of profitability, Microchip invites passionate professionals who challenge the status quo to be part of its continuing success.

Role Overview

The Networking and Connectivity Solutions Business Unit (NCS) based in Cork is expanding its R&D team with a focus on analog, digital, and communication system design. NCS delivers a wide range of networking ICs and software for applications from 10 Mbps up to 12.5 Gbps speeds, targeting primarily automotive and industrial sectors. The Cork team is currently seeking Senior Ethernet PHY designers to contribute to the development of advanced multi-gigabit T1 PHY products, working within a globally distributed team.

Key Responsibilities

• Architect and develop digital blocks for ASIC products specializing in serial communication PHY layers.
• Design RTL code using Verilog, SystemVerilog, or VHDL for digital communication components.
• Conduct functional verification and ensure bit-accurate matching against system models.
• Perform pre-silicon field-programmable gate array (FPGA) design emulation to validate logic.
• Collaborate closely with system architects, analog/mixed-signal designers, and verification teams to align development efforts.
• Coordinate with validation, firmware, and PTE teams to facilitate silicon bring-up and debugging activities.
• Lead design reviews, maintain comprehensive documentation, and provide technical guidance and mentorship to junior engineers.

Candidate Qualifications

• A bachelor's degree in science, engineering, or a closely related discipline is required.
• Minimum of 10 years' experience in digital ASIC design utilizing RTL methodologies.
• Proficiency in RTL development using Verilog, SystemVerilog, or VHDL.
• Strong understanding of high speed, asynchronous, and low power circuit design principles.
• Well versed in the digital integrated circuit development lifecycle and flow.
• Experience collaborating within global, cross-functional teams.
• Practical knowledge of functional verification methods using Verilog/SystemVerilog.
• Prior exposure to automotive and industrial Ethernet standards such as 802.3bp, 802.3ch, and 802.3cg is highly advantageous.
• Experience in mixed-signal design environments and familiarity with DSP algorithms and communication system concepts are considered beneficial.

Additional Information

Expected travel commitments range between 0% and 25%. Microchip maintains a strict policy regarding recruitment agencies and does not accept unsolicited resumes from them. Candidates are urged to apply directly.