NPU Staff Design Verification Engineer

About Qualcomm

Qualcomm is a global leader in technology innovation, dedicated to advancing next-generation experiences and enabling a smarter, connected future. Their Hardware Engineering team designs, verifies, optimizes, and tests a variety of electronic systems including circuits, Digital/Analog/RF/optical systems, and more to produce world-class products. Collaboration across various teams is key to developing effective solutions and achieving performance goals.

Position Overview

This position requires over 8 years of experience focusing on the design verification of Qualcomm's proprietary DSP/NPU intellectual property. The DSP team plays a crucial role in delivering high-performance DSP/NPU cores essential to Qualcomm’s multi-layer SoC strategy spanning mobile, AI, and automotive sectors. Qualcomm is a top fabless semiconductor company with $35 billion in annual revenue derived from chipsets and IP royalties.

Key Responsibilities

• Lead the design verification efforts of DSP IP by partnering with global DSP design teams including architecture, implementation, power, post-silicon, and back-end groups.
• Design and refine System Verilog/UVM testbench architectures.
• Introduce and enhance verification methodologies and automation to improve quality and efficiency continuously.
• Create detailed test plans, develop verification environments, and fulfill coverage requirements.
• Execute hands-on simulations and debug issues at IP, subsystem, and SoC levels.
• Complete all necessary IP-level verification activities ensuring commercial product success.
• Utilize a range of tools and techniques such as assertions, simulation, formal verification, HW-SW co-verification, constraint/HVL-based verification, simulation acceleration, and emulation daily.
• Manage gate-level simulation bring-up and conduct timing-accurate gate-level verification.
• Perform power-aware RTL verification and power-aware gate-level simulation.

Qualifications and Skills

• Minimum 12 years of experience in processor or ASIC design verification.
• Strong foundational knowledge in digital design, processor architecture, processor verification, and power-aware verification techniques.
• Advanced expertise in System Verilog testbench architecture and implementation.
• Preferred experience writing C-based and assembly-level test cases.
• Familiarity with power-aware design and verification using Unified Power Format (UPF) is advantageous.
• Understanding of advanced verification methods including formal verification and assertions is a plus.
• Proficient in gate-level simulation and debugging with 0-delay, timing-annotated, and power-aware capabilities.
• Hands-on experience with System Verilog/UVM and simulators from Synopsys, Mentor, or Cadence.
• Proficiency in scripting and automation using Perl, Python, Shell scripting, and Makefile/TCI is expected.
• Strong analytical and debugging capabilities combined with a solid grasp of object-oriented programming concepts.
• Experience with hardware verification languages like SystemVerilog testbench (OVM/UVM) and SystemC, and hardware description languages such as Verilog and SystemVerilog is preferred.
• Prior involvement in processor subsystem verification is desirable.
• Experience building validation suites and automation infrastructures.
• Excellent interpersonal and communication skills are essential.

Additional Information

Qualcomm is an equal opportunity employer committed to accessibility and providing accommodations for individuals with disabilities throughout the hiring process. Reasonable accommodations will be arranged upon request. Qualcomm expects employees to uphold company policies including confidentiality and security standards in accordance with applicable laws.

Note for recruiting agencies: Qualcomm does not accept unsolicited resumes or applications from agencies and does not pay fees related to such submissions. Only individuals seeking employment should use the company’s careers site.