Lead Design Engineer (Synthesis/LEC/CLP)

About Cadence

Cadence stands as a foremost leader in electronic design with over three decades of expertise in computational software. It embraces an Intelligent System Design approach delivering comprehensive solutions comprising software, hardware, and IP. Cadence serves some of the world's most innovative companies producing electronic products ranging from chips and boards to complex systems across markets such as consumer electronics, hyperscale computing, 5G communications, automotive, aerospace, industrial, and healthcare.

Why Work with Cadence?

• Opportunity to engage with pioneering technologies in a creative and impactful work atmosphere.
• Employee-focused policies supporting both physical and mental health, career growth, and tailored learning opportunities.
• A collaborative culture under the 'One Cadence – One Team' ethos ensuring collective success.
• Multiple platforms for personal and professional development aligned with employees' interests.
• A diverse, passionate workforce committed to excellence and community involvement daily.

Role Overview

As a Lead Design Engineer, you will drive hands-on execution involving synthesis, LEC (Logic Equivalence Checking), CLP, and UPF/power-intent flows targeting sophisticated ASIC/SoC projects. This position is execution-centric with expanding responsibilities, including independently debugging synthesis and LEC challenges, supporting CLP sign-offs, scripting for constraints and ECOs, and teamwork on complex escalations.

Key Responsibilities

• Perform LEC sign-off runs on design blocks and resolve NEQs and constraint inconsistencies.
• Execute and troubleshoot synthesis runs using Genus to enhance quality of results and address SDC/constraint problems.
• Provide support for CLP flows.
• Create and maintain ECO scripts alongside timing and power constraints for design blocks.
• Diagnose and document issues independently, escalating more complex/systemic problems appropriately.
• Collaborate cross-functionally with PD, DFT, and RTL teams to solve synthesis, LEC, and CLP closure challenges.
• Deliver clear status reports and technical summaries for internal progress monitoring.

Required Qualifications and Skills

• 5 to 8 years of practical experience in ASIC synthesis, logic equivalence checking, and/or low-power verification methodologies.
• Proficient with Cadence Genus synthesis tool and Conformal for LEC and/or CLP.
• Experience working with UPF (IEEE 1801) or CPF-based power intent specifications.
• Competent in scripting languages like Tcl, Perl, or Python, with familiarity in Unix/Linux environments.
• Strong foundation in digital design principles, static timing analysis fundamentals, and low-power architectures.
• Excellent communication abilities and capacity to work autonomously on assigned tasks.

Additional Details

Location options include Bangalore, Ahmedabad, and Pune divisions in India.

Educational requirement: BE/BTech/ME/MS/MTech in Electrical, Electronics, or equivalent fields.