High Level Synthesis Compiler Engineer

Overview

At Altera, the High Level Synthesis Compiler Engineer plays a critical role in developing and refining software tools that convert RTL and constraints into implementable FPGA designs. This includes enhancing compiler lowering, optimization, and its integration with the overall implementation, timing, and debugging workflow. The role emphasizes building dependable, scalable software solutions, mentoring fellow engineers, and collaborating closely with clients to ensure their complex design requirements are met effectively and practically.

Key Responsibilities

• Design and improve the FPGA compiler components including intermediate representation (IR), lowering processes, analysis and transformation passes, as well as optimizations focused on correctness and quality of results, while ensuring performance and memory scalability for large-scale designs.
• Engage directly with customers to comprehend their application needs, workflows, and definition of success; champion their requirements in terms of capability, quality, and turnaround times, proactively enhancing the compiler and design flow accordingly.
• Provide mentorship and coaching to engineers through code and design reviews, promoting ownership, sound design decisions, and high execution standards within the team.
• Create documentation that clarifies software behavior, existing limitations, and suggested workarounds for both internal teams and external users as appropriate.
• Maintain up-to-date knowledge of industry advancements in EDA, compiler technologies particularly LLVM/MLIR, FPGA design methodologies, and applicable standards.

Candidate Qualifications

• Possess a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a closely related discipline.
• Demonstrate more than eight years of professional experience in compiler construction, LLVM/MLIR integrated tooling, or FPGA/EDA implementation software development.
• Exhibit strong expertise in C++ for robust production-grade systems including areas of performance tuning, multi-threading, and managing extensive codebases.
• Have practical experience with MLIR and/or LLVM particularly in IR architecture, compiler passes, backend processing, or integration into comprehensive compiler or EDA flows.
• Show solid understanding of digital and FPGA design fundamentals, including LUTs, flip flops, block RAMs, DSP units, clocking schemes, timing analysis, and the impact of tool choices on design quality.
• Be knowledgeable about FPGA and ASIC implementation sequences such as synthesis, place-and-route, static timing analysis, constraints management, and familiar with typical design issues encountered in real projects.
• Be adept at collaborative communication and capable of translating client requirements into effective engineering solutions.
• Have a demonstrated capability to mentor engineers by providing constructive reviews, pair programming, and technical leadership.

Preferred Additional Experience

• PhD degree in relevant fields such as Electrical Engineering, Computer Engineering, or Computer Science.
• Experience with simulation, formal verification, debugging tools, or involvement with high-level synthesis flows and their mapping to backend toolchains.
• Track record of delivering software products used by external customers or large internal teams.

Compensation and Additional Information

The salary range offered for this position is approximately CAD 124,100 to CAD 179,700 annually, reflecting the Canadian market and dependent on the candidate’s expertise, qualifications, and other factors. Performance-based incentives complement the base salary, rewarding individual contributions and company success.

This job operates under Canadian employment regulations ensuring equal opportunity without discrimination based on various protected characteristics. The selection process uses artificial intelligence tools to evaluate candidates; Canadian work experience is not mandatory.

Job Details

Employment status is regular full-time with work location in Toronto, Ontario, Canada. The position operates during the standard first shift in Canada.