Foundation IP Memory Verification Engineer

About the Role

We are seeking enthusiastic and dedicated design engineers to join our Central Engineering Group. This elite team is responsible for developing foundational intellectual property (IP) for AI products, focusing on memory compilers, logic cells, and various custom macros built using the latest process technology. Positions are available across multiple experience levels.

Key Responsibilities

• Execute memory design validation for various custom memory macros and compilers.
• Carry out functional verification, analyze design discrepancies at root cause level, and collaborate to implement fixes.
• Conduct signal integrity evaluations to identify design vulnerabilities and suggest effective solutions.
• Perform transistor-level simulations to detect and address power-up or lock-up issues.
• Run electromigration (EM) and IR drop analyses/simulations to assess timing impact and internal margins.
• Verify timing characterization and internal margins through transistor-level simulations, discover any gaps, and ensure resolution.
• Carry out quality assurance and validation routines to ensure the accuracy of timing and power models.
• Create automation scripts to streamline verification processes and data analyses.
• Assist with silicon debugging activities and validate correlations to spice simulation models.
• Collaborate closely with memory designers to enhance memory characterization and validation workflows.
• Liaise with memory design leads, modeling leads, and management to define and implement comprehensive memory validation strategies.

Preferred Skills and Attributes

• Strong grasp of transistor-level circuit behavior and underlying device physics.
• Proficient in signal integrity, electromigration (EM) and IR analysis, along with reliability assessment techniques.
• Experienced in utilizing simulators, developing automation scripts, and handling various engineering tools.
• Knowledge of memory behavioral and physical modeling concepts is advantageous.
• Expertise in memory circuit design is a beneficial complement.
• Familiarity with Design For Test (DFT) schemes and chip-level integration processes is a plus.
• Excellent communication, interpersonal, and leadership abilities.
• Highly motivated, self-directed, and capable of managing multiple tasks simultaneously.
• A strong passion for solving complex engineering problems and eagerness to learn continuously.

Qualification Requirements

Candidates must hold a Bachelor's degree in Electronics or Computer Engineering and possess at least 5 years of experience related to memory circuit design and verification.