Design Verification Engineer

About the Role

We are looking for an experienced Design Verification Engineer with 5 to 15 years of hands-on involvement in live projects. This role requires developing effective functional verification environments and possessing excellent debugging capabilities. The candidate will work collaboratively within a cross-functional team to ensure the robustness and reliability of system verification processes.

Key Responsibilities

• Create and implement comprehensive functional verification environments incorporating monitors, checkers, scoreboards, and assertions.
• Apply deep knowledge of AMBA bus protocols, ARM CPU, and optionally PCI Express and Ethernet protocols to strengthen the verification process.
• Work closely with various teams to integrate and troubleshoot verification elements within the complete system architecture.
• Leverage scripting languages such as PERL, Python, Shell, and Makefile to automate and optimize verification routines.
• Engage actively in debugging sessions, providing critical insights and maintaining clear communication within the team.

Required Qualifications and Skills

• Strong expertise in System Verilog and UVM gained through practical work on live projects.
• Good understanding and experience with AMBA bus protocols and ARM CPU; familiarity with PCI Express and Ethernet protocols is advantageous.
• Proficiency in Unix-based systems along with skills in Configuration Management, Bug tracking, and verification dashboard tools.
• Experience in developing verification components like monitors, checkers, scoreboards, and assertions, with a sound grasp of verification methodologies involving random stimulus and functional coverage.

Preferred Attributes

• Ability to script in PERL, Python, Shell, or Makefile to facilitate automation and efficiency.
• Strong problem-solving abilities accompanied by effective debugging skills.
• Excellent interpersonal and communication skills fostering teamwork and collaboration.