ASIC RTL Architect

About the Company

Wipro Ltd is a leading global IT, consulting, and outsourcing company, employing over 170,000 people and operating in more than 175 cities across six continents. It assists clients in enhancing business operations through extensive industry knowledge, technology expertise, and a diverse service portfolio. With over 55 Centers of Excellence focused on emerging technologies, Wipro drives innovation and delivers valuable business outcomes while emphasizing integrity and sustainability.

Role Overview

Wipro is looking for a highly experienced ASIC RTL Architect with more than 15 years in RTL design and integration. This full-time position is based in Kochi, India, with hybrid working arrangements. The role requires expertise in micro-architecture, RTL coding, and subsystem integration, collaborating closely with cross-functional teams.

Key Responsibilities

• Design micro-architecture, partition blocks, and specify interface protocols based on system requirements.
• Manage performance, power, and area trade-offs along with ensuring RTL quality, including linting, CDC/RDC, synthesis, and constraint management.
• Lead integration at the subsystem and SoC levels, conducting design and code reviews.
• Collaborate with Design Verification, DFT, and Physical Design teams to address verification, timing, testability, and power concerns.
• Provide technical mentorship and guidance to RTL teams, serving as the escalation point for design challenges.
• Support activities related to emulation, FPGA prototyping, silicon bring-up, and failure analysis.

Candidate Qualifications

• At least 15 years of experience in RTL design and integration, with proven leadership in multiple tape-outs.
• Advanced knowledge of Verilog and SystemVerilog, accompanied by strong micro-architecture capabilities.
• Expertise in AMBA protocols (AXI/AHB/APB), Networks-on-Chip (NoC), and high-speed interfaces including PCIe, DDR/LPDDR, Ethernet, and USB.
• Strong understanding of low-power design techniques such as UPF, clock domain crossing, CDC/RDC, and timing-driven RTL development.
• Competency in using front-end EDA tools like linting, CDC analysis, synthesis, and static timing analysis, with scripting skills in Python, Perl, or Tcl.
• Excellent ability to communicate technical concepts effectively to clients and interdisciplinary teams.

Preferred Experience

• Integration experience with ARM or RISC-V subsystems.
• Knowledge of die-to-die communication, UCIe, and chiplet design architectures.
• Hands-on experience with post-silicon debugging.

Additional Information

Wipro emphasizes integrity and explicitly warns against employment scams that involve payment requests. Genuine Wipro job offers do not require any financial transactions from candidates.