ASIC Design Verification Engineer - ARM CPU Sub-System

About Tsavorite Scalable Intelligence

Tsavorite Scalable Intelligence is pioneering next-generation AI computing by integrating silicon, systems, and software into a cohesive architecture that includes general-purpose processing, AI acceleration, and scalable memory. Their solutions span from edge devices to data centers, aiming to advance AI capabilities in terms of power, efficiency, and accessibility. The company features a seasoned founding team with a strong track record in high-performance silicon and maintains engineering teams both in the US and India, looking for passionate and driven professionals to help shape future computing technologies.

Role Overview

The role focuses on design verification for server-class ARM CPU Sub-Systems at block and SoC levels. Responsibilities encompass developing detailed test plans, verification environments, and the implementation of checkers and scoreboards, along with executing tests and analyzing subsystem, chiplet, and multi-chiplet designs.

Technical Expertise Required

• Strong command over SystemVerilog/UVM methodology or proficiency in C/C++ for verification purposes with experience in IP, Sub-System, or SoC level verification.
• Experience creating UVM-based verification environments from the ground up.
• Capability to design testbenches and verification plans tailored to specific IP/Sub-Systems or functional domains.
• Skills in developing reusable bus functional models, stimulus sources, checkers, assertions, trackers, and coverage metrics.
• Familiarity with Coherent Mesh Network (CMN), System Memory Management Unit (SMMU), Generic Interrupt Controller (GIC), and ARM Chip-to-Chip protocols.
• Deep understanding of coherency concepts and the CHI protocol.
• Practical expertise with protocols such as CHI, APB, AXI, or CXS.
• Knowledge of the CPU Sub-System's integration with advanced Network-on-Chip (NoCs) and memory architectures.
• Hands-on verification experience on server-grade ARM CPUs.
• Comprehensive grasp of ARM Sub-System architecture (A-cores), including boot processes and debugging code execution.
• Proficiency with industry-standard verification tools such as Questa, VCS, and Visualizer during simulation and debugging.
• Utilization of random stimulus approaches combined with functional coverage and assertion-based verification strategies.

Key Responsibilities

• Collaborate with architects and RTL designers to fully understand high-level system requirements and specifications.
• Develop and execute thorough test and coverage plans aligned with architectural and micro-architectural designs.
• Manage design bring-up, verification environment setup, regression testing for feature validation, and detailed debugging of test failures.
• Support activities following silicon bring-up with troubleshooting and debugging.
• Report and track verification progress using metrics like test plan status, bug-tracking systems, and coverage documentation.

Educational & Experience Requirements

• A Bachelor’s or Master’s degree in Electrical or Electronics Engineering or Computer Science.
• 8 to 12 years of relevant professional experience.

Why Join Tsavorite?

• Take ownership and innovate within a team focused on next-generation computing technologies.
• Work alongside talented engineers dedicated to cutting-edge technology and impactful projects.
• Opportunity for personal and professional growth in a collaborative and innovation-driven culture.

Employee Benefits

• Competitive salary package aligned with industry standards.
• Comprehensive health insurance coverage for employees and eligible dependents.
• Access to stock options and ownership benefits.