AMS Verification Engineer

Job Overview

We are seeking an experienced AMS Verification Engineer based in Hyderabad to join our team. The ideal candidate will have a strong background in analog mixed-signal design and verification with hands-on experience in relevant methodologies and simulators.

Key Responsibilities and Skills

• Conduct verification of analog mixed-signal designs using SystemVerilog, UVM, Verilog-AMS, and Verilog-A.
• Apply mixed-signal verification methodologies effectively within projects.
• Utilize simulators such as Cadence Xcelium, Cadence AMS Designer, Synopsys VCS AMS, and Siemens Questa ADMS to run simulations and analyze results.
• Debug and resolve complex verification issues.
• Develop automation scripts leveraging Python, Perl, Shell, or TCL for testing and verification support.
• Implement assertions and coverage models, and manage regression testing suites.

Preferred Expertise

• Verification experience with high-speed interfaces including ADC/DACs, PLLs, SerDes, PMICs, and Sensor IPs.
• Knowledge of real-number modeling techniques and AMS verification acceleration approaches.
• Understanding of SoC-level integration and the verification process.
• Familiarity with low-power design verification concepts.

Qualifications

Candidates should hold a Bachelor's or Master's degree in Electronics & Communication Engineering, Electrical Engineering, or a related discipline, along with three to five years of AMS verification experience.