Senior Lead Static Timing Analysis (STA) Engineer

About Qualcomm and Role Overview

Qualcomm India Private Limited is a pioneering tech innovator dedicated to pushing technology limits to enable next-gen digital transformations. As a hardware engineer at Qualcomm, you will be involved in the design, optimization, verification, and testing of electronic systems across various layers including circuits, mechanical components, digital/analog/RF systems, test systems, FPGA, and DSP, contributing to high-performance, state-of-the-art products.

Key Responsibilities

• Collaborate extensively with RTL, CAD, DFT, and physical design teams to achieve SoC-level timing closure.
• Manage timing analysis and closure tasks for complex multi-GHz designs at block, cluster, and full-chip levels, ensuring frequency and power goals are met.
• Understand protocols such as DDR, PCIE, UCIE to define and validate timing constraints in partnership with RTL teams.
• Conduct static timing analysis (STA) across multiple modes, corners, and scenarios spanning hierarchical design levels.
• Investigate and resolve timing issues on critical frequency paths in collaboration with RTL and DFT teams, implementing logic and micro-architectural resolutions.
• Provide constructive timing guidance to physical design teams and generate/review timing ECOs to rectify setup, hold, noise, and cross-talk violations.
• Lead an STA team for assigned projects ensuring effective delivery.

Candidate Qualifications

• Bachelor’s degree with minimum 3 years, Master’s with 2 years, or PhD with at least 1 year of relevant experience in hardware engineering.
• Preferred candidates hold a Bachelor’s or Master’s in Electrical/Electronic Engineering with 5 to 9 years of hands-on experience in STA and timing closure.
• Strong practical knowledge of STA tools and timing closure processes for high-performance SoCs.
• Experienced in handling multi-clock, multi-domain SoC designs with stringent frequency targets using advanced sub-micron node technologies.
• Proficient in timing signoff across large CPU/SoC designs including multi-scenario analysis.
• Understanding of standard cell libraries, transistor basics, and worst-case corner selections for timing validation.
• Well-versed with industry-standard synthesis and tape-out workflows.
• Excellent communicator capable of liaising effectively with RTL, physical design, and CAD stakeholders.
• Deep understanding of timing phenomena like noise, cross-talk, and OCV/variation impacts on signal integrity.
• Familiar with STA tools such as Synopsys Tempus and Primetime.
• Experienced with scripting languages including Perl, TCL, and AWK.

Additional Information

Qualcomm is an equal opportunity employer committed to an accessible application and hiring process. Candidates with disabilities can request accommodations via the dedicated email for disability accommodations. Qualcomm maintains stringent policies for protecting proprietary company information and expects the same compliance from all employees.

Note for staffing and recruiting agencies: Qualcomm's career portal is solely for direct applicants. Unsolicited resumes or applications from agencies are not accepted. Contacts regarding this role should be directed to Qualcomm Careers.