Thrisha Medisetti

Electronics & Communication Engineering undergraduate · Embedded Systems and VLSI aspirant

Vijayawada, Andhra Pradesh, India

@trisha_medisetti

0 followers

🎓 B. Tech in Electronics and Communication Engineering at Prasad V. Potluri Siddhartha Institute of Technology · Graduating 2027

Follow Message

About

Electronics and Communication Engineering undergraduate with an 8.65 CGPA, FPGA-based RTL design experience, and hands-on exposure to Verilog HDL and Xilinx Vivado. Seeking an entry-level role in Embedded Systems or VLSI and interested in hardware-software co-design and firmware development.

Experience

FPGA-based VLSI Design Intern

Sense Semiconductors and IT Solutions Pvt. Ltd.

Apr 2025 – Jun 2025

Developed and simulated RTL modules using Verilog HDL and Xilinx Vivado; optimized FPGA design constraints and analyzed critical timing paths during synthesis and implementation; developed and executed Verilog testbenches for behavioral simulation and validation.

Education

2027

B. Tech in Electronics and Communication Engineering

Prasad V. Potluri Siddhartha Institute of Technology

Electronics and Communication Engineering (ECE) · 2023 – 2027

Electronics and Communication Engineering (ECE) · 2023 – 2027
2023

Intermediate Education

MJPAPBCWREIS Junior college Thanam

Science · 2021 – 2023

Science · 2021 – 2023
2021

SSC (Class X)

Govt. High School Thanam

2020 – 2021

2020 – 2021

Skills

3 to 6 months

RTL Design FPGA Design Verilog Hdl

<3 months

C I2C SPI Java VLSI UART SystemVerilog Embedded Systems PCB Layout Design Digital Electronics

Tools / apps / platforms

<3 months

Arduino The MathWorks MATLAB

Projects

SerDes Communication Protocol on Seven-Segment Display

Verilog HDL, Xilinx Vivado, FPGA

Designed and implemented a SerDes communication protocol with RTL logic for serial data transmission, deserialization, and seven-segment display interfacing on an FPGA. Implemented seven-segment decoder logic and validated functionality through simulation and waveform analysis.

Courses & certifications

C Programming Training · Spoken Tutorial

🏆 Achievements & awards

3rd Place, Code-HDL Technical Competition

Secured 3rd place by writing optimized, synthesizable Verilog code under strict time constraints, outperforming 50+ participants.

🎯 Hobbies & interests

Solving logical puzzles
Exploaring New Technologies

Explore the Broxer community

💬 Q&A Ask about roles, salaries and interviews — and help others. 👥 Circles Join discussions on skills, companies and industries. 📰 Feed Follow updates and insights from the community.