About
ECE undergraduate with a foundation in digital electronics, microprocessors and microcontrollers, C programming, and Verilog HDL. Interested in embedded systems and applying technical knowledge through practical electronics and chip design work.
Experience
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Internship on VLSI ESSENTIALSCouncil for Skills and Competencies (CSC INDIA)Jun 2026 – Jul 2026
Completed an internship in VLSI Essentials focusing on basic concepts of VLSI design, digital electronics, and semiconductor fundamentals. Gained exposure to VLSI design flow, logic gates, combinational and sequential circuits.
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Internship on VLSI ESSENTIALSCouncil for Skills and Competencies (CSC INDIA)Jun 2026 – Jul 2026
Completed an internship in VLSI Essentials focusing on basic concepts of VLSI design, digital electronics, and semiconductor fundamentals. Gained exposure to VLSI design flow, logic gates, combinational and sequential circuits.
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InternshipTara’s systemDec 2025 – May 2026
Completed online internship in VLSI / Electronics domain. Learned practical skills in digital design, Verilog simulation, and industry-standard tool usage.
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InternshipSRC E Solutions · Vijayawada
Gained practical exposure to electronics systems and real-time applications. Worked on basic hardware concepts and industry-oriented practices.
Education
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B. Tech in Electronics & Communication EngineeringLakireddy Bali Reddy Engineering CollegeElectronics & Communication Engineering · Jul 2024 – May 2027
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Diploma in Electronics & Communication EngineeringGovernment Polytechnic, VijayawadaElectronics & Communication Engineering · Jun 2021 – Apr 2024
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Secondary School EducationS.T.V.R.M.C. High SchoolJun 2016 – Apr 2021
Skills
Tools / apps / platforms
Projects
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Implementing SPI Communication Protocol using VerilogVerilog HDL, Xilinx Vivado, ModelSim
Designed and implemented SPI communication protocol for serial communication between master and slave. Simulated and verified data transfer using MOSI, MISO, SCLK and SS signals.
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Implementing SPI Communication Protocol using VerilogVerilog HDL, Xilinx Vivado, ModelSim
Designed and implemented SPI communication protocol for serial communication between master and slave. Simulated and verified data transfer using MOSI, MISO, SCLK and SS signals.
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Implementing SPI Communication Protocol using VerilogVerilog HDL, Xilinx Vivado, ModelSim
Designed and implemented SPI communication protocol for serial communication between master and slave. Simulated and verified data transfer using MOSI, MISO, SCLK and SS signals.
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Intelligent Pesticide Sprinkling System Determined by the infected leaf of a plantRaspberry Pi 5, MobileNet, thermal sensing, RTK GPS
Developed an AI-powered drone-based pesticide sprinkling system for selective spraying and reduced pesticide usage. Enabled early crop infection detection and precise localization to improve agricultural efficiency and farmer safety.
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Smart Attendance System using RFIDRFID
Designed an attendance system using RFID technology to automate student attendance.
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Intelligent Pesticide Sprinkling System Determined by the infected leaf of a plantRaspberry Pi 5, MobileNet, thermal sensing, RTK GPS
Developed an AI-powered drone-based pesticide sprinkling system for selective spraying and reduced pesticide usage. Enabled early crop infection detection and precise localization to improve agricultural efficiency and farmer safety.
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Intelligent Pesticide Sprinkling System Determined by the infected leaf of a plantRaspberry Pi 5, MobileNet, thermal sensing, RTK GPS
Developed an AI-powered drone-based pesticide sprinkling system for selective spraying and reduced pesticide usage. Enabled early crop infection detection and precise localization to improve agricultural efficiency and farmer safety.
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Smart Attendance System using RFIDRFID
Designed an attendance system using RFID technology to automate student attendance.
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Smart Attendance System using RFIDRFID
Designed an attendance system using RFID technology to automate student attendance.
Courses & certifications
- Industrial 4.0 and Internet of Thing · NPTEL
- Cisco Certification · Cisco
- Verilog HDL Completion course
- Maveen Silicon · chip design
- VLSI Essential Internship · CSC India (APSCHE)
- Industrial 4.0 and Internet of Thing · NPTEL
- Industrial 4.0 and Internet of Thing · NPTEL
- Cisco Certification · Cisco
- Cisco Certification · Cisco
- Verilog HDL Completion course
- Verilog HDL Completion course
- Maveen Silicon · chip design
- Maveen Silicon · chip design
- VLSI Essential Internship · CSC India (APSCHE)
- VLSI Essential Internship · CSC India (APSCHE)
🏆 Achievements & awards
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Smart India Hackathon (SIH) Participant · 2025
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1st Prize - College Level Coding Contest · 2026
For developing a Smart Billing System
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Main Coordinator - Udbhavana (Project Expo), LAKSHYA 2026 · 2026
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Project Expo Participant - VR Siddhartha Engineering College · 2026
⚽ Extracurricular activities
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Dancing
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Acting
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Anchoring