Sunny Thakral

Project Coordination · PMO Support · Technical Implementation

Rajpura, Punjab, India

@sunny_thakral

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🎓 Bachelor of Engineering in Electronics & Communication at Chitkara University · Graduating 2027

About

Electronics & Communication Engineering student transitioning into project coordination and PMO operations, with hands-on exposure to robotics installation and commissioning workflows at GreyOrange. Brings strong analytical problem-solving, technical execution support, milestone tracking, documentation, and cross-functional coordination skills.

Experience

Installation & Commissioning Intern

GreyOrange · Gurgaon, India

2026 – Present

Support on-site and operational deployment workflows for automated robotics systems, tracking hardware-software commissioning milestones and verifying installation checklists. Coordinate across deployment technicians, operations associates, and engineering leads to facilitate daily work progress, communicate schedule changes, and track action items. Assist in recording, categorizing, and following up on field installation issues, maintaining documentation that mitigates go-live blockers and ensures timely closure of operational snags. Support preparation of site readiness documentation, commissioning logs, and structured progress updates for operational stakeholders, ensuring alignment with standardized delivery procedures.

Education

2027

Bachelor of Engineering

Chitkara University

Electronics and Communication Engineering (ECE) · 2023 – 2027

Electronics and Communication Engineering (ECE) · 2023 – 2027

Skills

6 to 12 months

Documentation Task tracking Status Reporting Milestone Tracking Risk identification Project Coordination

<3 months

C SQL TCL FPGA ESP32 STM32 Python Verilog LTSpice PMO Support Xilinx Vivado Cadence Innovus Cadence Virtuoso Root Cause Analysis Standard Operating Procedures Installation And Commissioning

Tools / apps / platforms

<3 months

Linux Tableau Microsoft Excel Microsoft Windows Microsoft Power BI

Projects

Two-Stage CMOS Operational Amplifier Design

Cadence Virtuoso

Engineered and simulated analog schematics to meet stringent design criteria, validating ~64 dB open-loop gain, 9 MHz Gain Bandwidth, and a robust 156° phase margin.
Comparative SRAM Performance Analysis (CMOS vs. CNTFET)

Coordinated simulation runs and compiled structured comparative analyses evaluating read/write delay, Static Noise Margin (SNM), power dissipation, and Power-Delay Product (PDP). Validated critical design margins, reporting a 69% reduction in read delay and a read SNM of ~161 mV.
16-Bit Pipelined RISC Microprocessor Implementation

Cadence Genus, Innovus, Xilinx Vivado

Planned and delivered an end-to-end RTL-to-GDSII digital flow, managing multi-stage deliverables from synthesis to physical design verification. Verified performance baselines to achieve a 745 MHz post-synthesis frequency, 7.299 ns positive Worst Negative Slack (WNS), and zero Design Rule Check (DRC) violations through static timing analysis and constraints optimization.

Courses & certifications

CeNSE Winter School · IISc Bangalore
RTL-to-GDSII Design Flow · NIELIT Gorakhpur
Entrepreneurial Thinking · IUCEE
VLSI Design Flow · NPTEL
Data Analytics · Cisco Networking Academy

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