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JV

Javvadi Om Sree Vagdevi

VLSI trainee · Verilog HDL, SystemVerilog, UVM

Hyderabad, Telangana, India

@sree_vagdevi

LinkedIn

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🎓 PGCP Diploma - VLSI at cdac · Graduating 2026

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About

Motivated and detail-oriented VLSI trainee with hands-on exposure to digital design, hardware testing, and communication protocols. Seeking an entry-level role in VLSI design/verification to apply technical skills and continue learning.

Experience

  • Apprentice
    BHEL R&D · Hyderabad
    Dec 2024 – Dec 2025

    Assisted senior engineers in circuit design, simulation, schematics preparation, and PCB layout; performed soldering and connectivity testing; prepared BOM and verified component ratings; supported schematic design and quality checks; used hardware testing equipment; maintained technical documentation.

Education

  • PG DIPLOMA
    CDAC
    VLSI · Feb 2026 – Aug 2026
  • Bachelor of Technology
    SRK Institute of Technology · JNTUK
    Electronics and Communication Engineering · Aug 2021 – 2024
  • Diploma
    Krishnaveni Polytechnic
    Electronics and Communication Engineering · 2018 – 2021

Skills

<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.
C UVM Python Verilog Hdl SystemVerilog Digital Design Communication Protocols

Tools / apps / platforms

6 to 12 months 6 to 12 months Most of a year behind them.
KiCad OrCAD Capture
<3 months <3 months Just getting started - under three months. This is also what shows when a level has not been set.
Linux ThingSpeak Visual Studio Code VMWare Workstation Cisco Packet Tracer

Projects

  • Detecting Environment Pollution Using IoT
    ThingSpeak

    Developed an IoT-based pollution monitoring system using wireless sensors, transmitted real-time environmental parameters to the cloud, and displayed pollution levels on a mobile dashboard.

  • Warehouse Design Using Collapsed Core Architecture
    Cisco Packet Tracer

    Designed a collapsed core network architecture to reduce complexity and improve scalability, using routers, switches, and topology simulation.

  • Design and Comparative Analysis of I2C and SPI Communication Protocols Using Verilog HDL
    Verilog HDL, ModelSim, QuestaSim

    Designed and implemented I2C and SPI communication protocols, developed FSM and control logic, and verified RTL functionality using testbenches and waveform analysis.

Courses & certifications

  • CISCO Certificate Network Associate · Techno Spark IT Solution
  • Internet of Things (IoT) Internship Program · SRC e-Solutions
  • Embedded Developer Virtual Internship

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